ADAV4622
Rev. B | Page 24 of 2
8
LRCLK
BCLK
SDO0
MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
0
7068-
022
Figure 26. I
2
S Mode
LRCLK
BCLK
SDO0
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
070
68-
02
3
Figure 27. Left-Justified Mode
LRCLK
BCLK
SDO0
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
07
068-
024
Figure 28. Right-Justified Mode
PWM OUTPUTS
In the ADAV4622, the main outputs are available as four PWM
output channels, which are suitable for driving Class-D amplifiers.
PWM_Ready is a status pin used to signify that the ADAV4622
PWM outputs are in a valid state. During PWM power-up and
power-down, this pin remains low to signify that the outputs
are not in a valid state. The output power stage should remain
muted until this pin goes high. This functionality helps to
eliminate pop/click and other unwanted noise on the outputs.
PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM
MODULATOR
PWM
MODULATOR
PWM
MODULATOR
+
–
+
–
+
–
PWM4A
PWM_READY
PWM4B
PWM
MODULATOR
+
–
07
06
8
-02
6
Figure 29. PWM Output Section
Each set of PWM outputs is a complementary output. The
modulation frequency is 384 kHz, and the full-scale duty cycle
has a ratio of 97:3.
Full details on the use of the PWM outputs are available upon
request. Contact a local Analog Devices sales representative for
more details.
HEADPHONE OUTPUTS
There are two stereo headphone amplifier outputs capable
of driving 32 Ω loads at 1 V rms. HPOUT1 is shared with
AUXOUT4, and HPOUT2 is shared with AUXOUT2, as shown
in Figure 30.
AUXOUT2R
AUXOUT2L
PA
HPOUT2L
HPOUT2R
DAC
07
06
8-
02
7
AUXOUT4R
AUXOUT4L
PA
HPOUT1L
HPOUT1R
DAC
Figure 30. Headphone Outputs Section
I
2
S DIGITAL AUDIO OUTPUTS
One I
2
S output, SDO0, uses the same serial clocks as the serial
inputs, which are BCLK1 and LRCLK1 by default. If an addi-
tional digital output is required, an additional pin can be
reconfigured as a serial digital output, as shown in Figure 31.
SDO0
R
L
R
L
S/PDIF
OUTPUT
SPDIF_OUT (SDO1)
I
2
S OUTPUT
INTERFACE
BCLK1
LRCLK1
0
7068-
028
Figure 31. I
2
S Digital Outputs
