UG-600
Evaluation Board User Guide
EVALUATION BOARD SETUP INSTRUCTIONS
To setup the
, the user needs a 5 V power
supply, differential analog input source, and a PC with a USB
port. Use a single 5 V, 1 A current rating for the power supply.
For full evaluation of the
, a ±20 V supply is
required. This power supply facilitates the generation of a
10 V rms signal as well as a VBAT supply for microphone
diagnostics.
JUMPER SETTINGS
See Figure 2 for the setup of the evaluation board connections.
Connect the positive power supply lead to J5 and the 0 V lead to
J4 of the evaluation board. Do not turn the power supply on at
this time.
In the power supply section, take the following steps:
1.
Set Jumpers J13 and J14 to the
INT
position.
2.
Set Switch S1 to the
ON
position.
3.
Set Jumper J10 to the desired IOVDD supply, 3.3 V, or
1.8 V.
4.
Set Jumper J11 to the
INT
position for the internal
IOVDD.
5.
Set Switch S2 to the
ON
position to turn on the 1.8 V
regulator.
In the daughter board section, take the following steps:
1.
Install Jumpers J16, J21, J24, and J33. The J16 jumper
provides the AVDD. Jumpers J21 and J24 provide the 3.3 V
power supply to the boost converter. The J33 jumper
provides the IOVDD to the
In the PLL and MCLK section, take the following steps:
1.
Select the master clock source. The evaluation board
provides three options for providing the master clock to
the ADC. The three options include the following: the on-
board 12.288 MHz oscillator, the external source at JP9,
and the SMA Connector J52.
2.
To use the on-board oscillator, install Jumper JP11. To shut
down the oscillator, remove Jumper JP11.
3.
Set Jumper J50 in the
OSC
center position.
4.
Alternatively, if the external master clock is available, it can
either be connected at J52 as a coaxial 50 Ω SMA
connector, or at JP9 as a 2-way header (0.1” pitch). If using
JP9 as the source, install J50 in the
PSIA
position. If using
J52 as the source, install J50 in the
SMA
position.
5.
The MCLK is level shifted to the required IOVDD. By default,
the level shifted master clock is used. Set Jumper J43 to the
IOVDD
position. Alternatively, if direct MCLK pin access
is needed, set J43 to the
3V3
position. In this case, ensure
that the master clock supplied to the
correct IOVDD level.
6.
Two options are provided for the PLL filter, MCLK mode
or LRCLK mode. By default, the MCLK mode is selected
by installing Jumper J44 in the
MCLK
position. If the
LRCLK mode is required, set J44 in the
LRCLK
position.
In the I
2
S output section, take the following steps:
1.
Determine the serial data format used for the ADC output.
Either I
2
S/left justified (LJ)/right justified (RJ)/TDM
format or SPDIF format are available.
For I
2
S/LJ/RJ/TDM format, take the following steps:
1.
Set LK3 and LK5 to the
I
2
S
position.
2.
Set LK1 and LK2 to the
I
2
S
position.
3.
Set Switch S13 to the
MASTER
position if the
the serial audio port. Alternatively, it can be set to the
SLAVE
position; however, in this case, both the LRCLK
(frame clock) and the BCLK (bit clock) must be provided
from an external source.
4.
The buffered serial output is available on the J26 (4-way
dual row, 0.1” pitch) header. Alternatively, the direct
(unbuffered)
serial outputs are available on the
J25 (8-way dual row, 0.1” pitch) header.
For SPDIF format, take the following steps:
1.
Ensure LK3 and LK5 are set to the
SPDIF
position.
2.
Ensure LK1 and LK2 are set to the
SPDIF
position.
3.
Ensure LK4 is set to the desired serial data pair. Either
Pair 1 (Ch1 and Ch2) or Pair 2 (Ch3 and Ch4) can be
selected because only 2-channel SPDIF output is available
on the evaluation board.
4.
Ensure LK6 is set to the
SPDIF
position which provides
the MCLK to the SPDIF transmitter.
5.
The SPDIF output is available on U16 as an optical form or
on J35 as a coaxial form.
For the I
2
C/SPI control section, take the following steps:
1.
Slide Switches S3, S4, and S5 are used to set the control
communication protocol for the
For I
2
C protocol, take the following steps:
1.
Set Switches S3, S4, and S5 to the
I
2
C
position.
2.
Ensure JP6 is not installed.
3.
The device address for the
is set using
Switch S9. The possible 7-bit device addresses are 0x11,
0x31, 0x51, or 0x71. The
board is set for the 0x71 address.
4.
The 20-way (10-pin, dual row, 0.1” pitch), Shrouded
Connector J8 is used to connect the supplied USBi.
Alternatively, any other I
2
C master controller can be
connected at J8 to control the
5.
The Analog Devices, Inc., USBi is the quickest way to set
the
standalone GUI or SigmaStudio™ software.
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