Quick Start Guide
AD9739A-EBZ
Rev. A | Page 5 of 8
SPI SOFTWARE
The SPI software is broken up into numerous sections. Several of them are described here, as they pertain to the evaluation board. For
complete descriptions of each SPI register, see the AD9737A/AD9739A datasheet. In the interest of continuous quality improvements, the
images below may not exactly match your version of the software.
SPI Settings and Powerdown/Reset
These bits (shown in Figure 12) control the operation of the SPI port on the AD9737A/AD9739A, as well as
the master reset and individual power-down bits. Changing the
SDIO DIR
or
DATADIR
bits will cause the
SPI application to stop functioning correctly. Do not change these bits. The Reset button is “sticky”, that is,
the part will stay in reset for as long as the button is enabled. To reset the part, set this bit, run the SPI
application, then unset this bit and run the application again.
Controller Clock Controls and Analog FS controls
The Controller Clock controls enable the Mu Controller and LVDS controllers. For normal operation,
both of these should be enabled. The
Clock GEN PD
switch powers down the clocking structure, and
should be left disabled for normal use.
The DAC current ouput has an adjustable full-scale value. The
FSC Set
option allows for this adjustment.
After running the SPI application, the full-scale current in miliamps will be displayed here.
Decoder Controller and IRQ Controls
Cross Control
Mu Controller Clock Enable: Register 0x02 Bit 0
LVDS Controller Clock Enable: Register 0x02 Bit 1
Analog Full-Scale Setting (10 bit Gain DAC 10-30mA adjustment): Register 0x06 bit 0:8, Register
0x07 bits 0,1
Decoder Mode: Register 0x08 Bits 0,1
0x0 – Normal Mode
0x1 – Return to zero (RZ) Mode
0x2 – Mix Mode
CLKP Offset Setting: Register 0x24 Bits 0-3
CLKP Direction Bit: Register 0x24 Bit 4
CLKP Offset Setting: Register 0x25 Bits 0-3
CLKP Direction Bit: Register 0x25 Bit 4
Damp: Register 0x25 Bits 7
Figure 9
Figure 10
Figure 11
Figure 12