Analog Devices AD9273, Руководство пользователя

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AD9273
Rev. B | Page 32 of 48
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
A
)
due only to aperture jitter (t
J
) can be calculated by
SNR Degradation = 20 × log 10[1/2 × π × f
A
× t
J
]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 60).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9273.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit
www.analog.com ).
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
NR (
d
B
)
0.25ps
07
03
0-
0
38
Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 62, the power dissipated by the AD9273 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
0
0
SAMPLING FREQUENCY (MSPS)
S
UP
P
L
Y
CURR
E
NT
(
m
A)
250
200
150
100
50
10 30 20 40 50
07
03
0-
03
2
I
AVDD1
, 50MSPS SPEED GRADE
I
AVDD1
, 40MSPS SPEED GRADE
I
AVDD1
, 25MSPS SPEED GRADE
I
DRVDD
Figure 61. Supply Current vs. f
SAMPLE
for f
IN
= 5 MHz
120
80
0
SAMPLING FREQUENCY (MSPS)
P
O
W
E
R
/C
HANNE
L
(
m
W
)
10 30 20 50 40
115
110
105
100
95
90
85
50MSPS SPEED GRADE
40MSPS SPEED GRADE
25MSPS SPEED GRADE
07
03
0-
03
1
Figure 62. Power per Channel vs. f
SAMPLE
for f
IN
= 5 MHz
The AD9273 features scalable LNA bias currents (see Register 0x12
in Table 17). The default LNA bias current settings are high.
Figure 63 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended to adjust the LNA
offset using Register 0x10 (see Table 17) when the LNA bias
setting is low.
0 20 40 60 80 100 120 140 160 180
HIGH
L
NA BI
AS
S
E
T
T
IN
G
MID-HIGH
MID-LOW
LOW
TOTAL AVDD2 CURRENT (mA)
0
70
30
-11
9
Figure 63. AVDD2 Current at Different LNA Bias Settings, AD9273-40