Analog Devices AD9142A-M5372-EBZ, Быстрый старт

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Rev 07 Aug 2013 10:33 | Page 4
a. Click “Reset DAC” button on the “Quick Start” tab.
b. Click “Restore Registers from File” and select the configuration file “Config_8X.csv”. This will
configure the registers with correct values under the condition we are testing.
c. Click “AD9516 Update” button. This step updates the clock distribution chip AD9516 with the
settings that were loaded from the configuration file.
d. There may be a few registers highlighted in red. The red highlights mean mismatches between the
SPI read and write values in the software. Clicking “Read All Registers” reads back all the current
values in the registers, which should resolve the highlights.
e. Toggle register “FIFO SPI RESET REQUEST”. The FIFO level readback registers (INTEGRAL and
FRACTIOANAL) should now match the FIFO level request registers.
f. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG >
DPGDownloader). Ensure that the program detects the AD9142A, as indicated in the “Evaluation
Board” drop-down list, and select it. For this evaluation board, LVDS is the only valid Port
Configuration, and it will be selected automatically. The “DCO Frequency” window should show the
correct data rate (350 MHz). The actual detected frequency may not be exactly 350 MHz but it should
be stable and very close to it as shown in Figure 4.
Figure 4 DPG Downloader Panel
g. Click on “Add Generated Waveform”, and then “Single Tone”. As shown in Figure 5, A Single Tone
panel will be added to the vector list. Enter the sample rate, in this case 350 MHz and the desired
frequency, 50MHz. Enter the digital amplitude. In this case we use -14dBFS. Check the “Generate
Complex Data (I & Q)” box and uncheck the “Unsigned Data” box. Select the In-Phase data vector in
the “I Data Vector” drop down menu and the Quadrature data vector in the “Q Data Vector”.