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Evaluation Board User Guide 

UG-073

 

Rev. 0 | Page 7 of

 12

 

EVALUATION BOARD SOFTWARE: QUICK START PROCEDURES 

This section provides quick start procedures for using the AD911x 
or AD971x. Both the default and optional settings are described. 

CONFIGURING THE BOARD 

Before using the software for testing, configure the evaluation 
board as follows: 

1.

 

Connect the evaluation board to the DPG2 evaluation 
board.  

2.

 

Connect the AD911x or AD971x evaluation board to the 
PC with a USB cable (ConnectorXP2 USB/BRD PWR). 
The LED XD1 should turn on. If it does not turn on, refer 
to the Power Circuitry section and configure the board 
with the default setting.  

3.

 

Connect a clean signal generator with low phase noise to 
provide an input signal to the clock distribution source 
input, J10. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable 
to connect the signal generator. 

USING THE SOFTWARE FOR TESTING 

Set Up the DPG2 Software 

After configuring the board, set up the DPG2 by following  
these steps: 

1.

 

Open 

DPGDownloader

 (

Start > Programs > Analog 

Devices > DPG > DPGDownloader

).  

The program should automatically recognize and display 
the evaluation board, such as the 

AD9717

 used in this 

example,

 

in the drop-down menu for the 

Evaluation 

Board

, as shown in Figure 3  

2.

 

Select 

LVCMOS-3.3V (DCO)

 for the 

Port Configuration

 

as the DPG2 data clock input, also shown in Figure 3. 

086

98

-00

3

 

Figure 3. DPG2 Board Configuration 

3.

 

Open the AD911x or AD971x SPI software (

Start > 

Programs > Analog Devices > AD9717 > AD971x SPI

). 

4.

 

Select the clock dividers for the data clock going to the 
DPG2, and for the clock going to the DAC. The divider 
ratio for the DAC clock should be double the ratio for the 
data clock as shown in Figure 4

08

69

8-

00

4

 

Figure 4. AD9512 Clock Divider Setting 

 

The clock going to the DAC should be no greater than 
125 MHz. When the AD9512 configuration is complete, 
verify the clock frequency output to the DPG2 in  
Figure 3. The frequency displayed represents the frequency 
of the clock sent to the DPG2. It should be no greater than  
250 MHz. 

5.

 

In the DPG2 window (see Figure 5), select 

Add Generated 

Waveform

, and then select 

Single Tone

. A single tone 

panel is added to the vector list. Enter a clock frequency of 
125 MHz for 

Data Clock Frequency

.  

Note that this frequency is half of the frequency in Figure 3 
for 

Data Clock Frequency

 as the data clock sent to the 

DPG2 is twice the rate of the DAC.

 

However, the vector 

generation is done using the DAC clock (data clock/2) (see 
Figure 4).

  

6.

 

Make the following entries: 

 

Enter 10 MHz as the 

Desired Frequency

 of the tone.  

 

The 

DAC Resolution

 should be set at the r

esolution 

of the IC 

selected (14 bits for th

AD9717

 an

AD9117, 12 bits for th

AD9716

 and AD9116, and  

so on).  

 

Keep 

Record Length

 at 16384 

 

The digital scaling back of the tone can be done by 
changing the

 Amplitude

 (defaults to 0 dB).  

 

Ensure that 

Unsigned Data

 and 

Generate Complex 

Data (I & Q)

 are selected.  

See Figure 5 for the appropriate settings.  

08698-

005

 

Figure 5. Single Tone Generation 

7.

 

In the lower portion of the screen, select 

1I / 1Q: Single 

Tone

 as the 

Data Vector

, choosing the appropriate in-

phase and quadrature data for the I and Q vectors, shown 
in Figure 6. The other options can be left at their default.  

Содержание AD911 Series

Страница 1: ...ncluding register defin itions The DPG2 user guide is also available for assistance with vector generation and loading GENERAL DESCRIPTION This user guide describes the AD911x and AD971x evaluation boards which provide all of the support circuitry required to operate the AD911x and AD971x in their various modes and configurations The application software used to interface with the devices is also ...

Страница 2: ... Description 1 Revision History 2 Evaluation Board Hardware 3 Power Supplies 3 Clock Signals 3 Input Signals 3 Output Signals 4 Default Operation and Jumper Selection Settings 4 Evaluation Board Software Quick Start Procedures 7 Configuring the Board 7 Using the Software for Testing 7 ESD Caution 12 REVISION HISTORY 3 10 Revision 0 Initial Version ...

Страница 3: ...isted TP5 AVDD TP12 TP24 CVDD and TP13 TP8 DVDD with grounds at TP6 TP14 TP23 TP4 and TP9 All voltages should show a reading of around 3 3 V with the factory default jumper settings as mentioned These voltages can be changed to 1 8 V by switching JP22 JP26 JP29 JP88 and JP89 to shunt Pin 2 and Pin 3 Alternatively external power supplies can be used to supply the AD911x or AD971x and its supporting...

Страница 4: ...rs JP22 JP26 JP29 JP88 and JP89 see Figure 2 Alternatively external power supplies can supply all the on board components The choice between internally or externally regulated power supplies can be done individually per power supply by two position jumpers JP6 JP10 JP54 JP15 and JP78 see Figure 2 These regulated voltages are then connected to on board filters to be used by the components on board ...

Страница 5: ...the SPI software see Section VI in the SPI section On the evaluation board three jumpers for each DAC select the configuration and maximum DAC current as shown in Table 3 Table 3 DAC Current Full Scale Jumpers DACI DACQ Jumper Setting Full Scale Current Jumper Setting Full Scale Current JP9 On JP8 Off JP7 Off AD971x 4 mA AD911x 20 mA JP20 On JP16 Off JP21 Off AD971x 4 mA AD911x 20 mA JP9 Off JP8 O...

Страница 6: ... Load Resistor Default On Chip Load Resistors R57 R50 On Off JP32 JP33 JP34 JP35 Off On RLOAD Load Resistor R57 for IDAC R50 for QDAC 62 5 Ω for AD911x 500 Ω for AD971x In the load mode configuration proposed the output voltage for each DAC can be calculated using the formula VOUTPUT RLOAD IOUT Pin Mode The AD971x and AD911x evaluation boards have the capability to function in pin mode This bypass...

Страница 7: ...dividers for the data clock going to the DPG2 and for the clock going to the DAC The divider ratio for the DAC clock should be double the ratio for the data clock as shown in Figure 4 08698 004 Figure 4 AD9512 Clock Divider Setting The clock going to the DAC should be no greater than 125 MHz When the AD9512 configuration is complete verify the clock frequency output to the DPG2 in Figure 3 The fre...

Страница 8: ...priate codes in the SPI Settings for the external shunts are listed in the Analog Outputs section To use the internal bias resistors see the SPI section for information on the settings that must be changed to fully enable and set these resistors SPI Software The SPI software consists of various small sections which are described here as they relate to the evaluation board Once the setting of the p...

Страница 9: ... DAC Set internal IRCM and QRCM values Set I Q auxiliary DAC code Set internal IGAIN and QGAIN values Section X Section VIII This section of the SPI configures the INL DNL calibration of the main DAC This section of the SPI configures the retimer of the DUT as follows Automatic or manual retimer selection Readback or setting of retimer phase 08698 007 SECTION I SECTION III SECTION IV SECTION V SEC...

Страница 10: ...re shown in Table 8 Table 8 Internal Resistor Options and SPI Code IRSET QRSET Value Code 16 kΩ 000000 default 32 kΩ 011111 8 kΩ 100000 16 kΩ 111111 Using the AUX DACs For LO Suppression To completely suppress the LO when using the modulator in the signal chain automatic VIs can be used to sweep the codes for all of the range and offset settings of the DAC Section IX of Figure 7 contains all of th...

Страница 11: ...3 J14 J19 and J23 which removes the resistors from the parallel connection with 1 kΩ 100 Ω at the input of the modulator to measure the individual resistances of those components Check if the resistance values are still incorrect and if so change out for the appropriate values listed above If not try resoldering the jumpers and test again to make sure there was not a problem with the previous conn...

Страница 12: ...REQ 19 93MHz 105 08MHz 16 25dBm 33 15dBm EXT REF DC COUPLED 1 2 Figure 9 DAC Output Spectrum ESD CAUTION Evaluation boards are only intended for device evaluation and not for production purposes Evaluation boards are supplied as is and without warranties of any kind express implied or statutory including but not limited to any implied warranty of merchantability or fitness for a particular purpose...

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