Amtelco infinity series, Техническое руководство

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The H.110 Bus & Clock Modes • 6-5 •
The H.110 Basic Rate ISDN Board
When operating in secondary master mode, submodes 0-3 are valid, and
the arguments a and bb are the same as when operating as a primary
master.
6.2.4 Clock Fallback
The H.110 Specification details a scheme for automatically recovering from
a clock failure. One of the CT bus clocks, either A or B is designated the
master clock. The other clock is the secondary master and is generated by
a different board than the primary clock. While the primary clock is valid,
the secondary clock is locked to it. If the primary clock should fail, the
secondary clock takes over using a local oscillator, CT_NETREF_1,
CT_NETREF_2, or a local network as the source. Boards that are slaves
should automatically fall back to the secondary clock. After a failure of the
master clock, system software should designate new primary and secondary
clocks. The new primary may be the previous secondary clock master.
For Infinity Series H.110 boards, this will involve sending a set clock
command with the new primary clock information.
When an Infinity Series board is set for automatic fallback, the board will
automatically switch to the secondary clock if the primary clock fails.
When this occurs, the board will send an “EC” message indicating the
failure. When the application designates a new primary master, it should
send a new clock mode command to the board even though auto-fallback
may have occurred.
6.2.5 Clock Errors
If the board detects a problem with the clocks, it will generate a clock error,
which notifies the application that it should take appropriate action. Clock
errors are reported in the Clock Error Bit message,
ECxx where the xx is
a hexadecimal value in which each bit identifies the specific error. A value
of 1 indicates an error condition. The bits are as follows:
bit Error Description
0 CT bus clock A