Ametek UPLC CU44-VER04, Руководство по применению

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Page 3–8
UPLC™ Application Manual
receiver’s trip positive output. The other wave, which has positive
output during the negative half-cycle of the sequence current net-
work, is compared to the receiver’s trip neg. output in a second
comparison circuit.
On internal faults, the positive half-cycle of the local square wave
lines up with the received trip positive output to provide an AND-
1 output. On the negative half-cycle, this local square wave lines
Figure 3–6. Basic Operation of the Dual
Phase Comparison Pilot Relaying System.
up with the received trip negative
output to provide an AND-2 out-
put. If an arming signal is received
(FD2 and/or 21P) and either AND-
1 or AND-2 output exists for 4ms,
an input to the trip flip flop initi-
ates breaker tripping. The same
operation occurs at both terminals,
tripping breakers 1 and 2 simulta-
neously on either half-cycle of
fault current.
For tripping, both the trip positive
and trip negative frequencies must
be transmitted through the internal
fault via power-line carrier chan-
nels. If these frequencies are not
received, the receiver detects a loss
of channel and clamps both out-
puts to a continuous positive state.
This loss of channel clamp enables
both comparison circuits, allowing
the system to trip on the local
square wave input only. After
150ms, the system output clamps
these to the zero state. At this
point, the system cannot trip and is
locked out. An alarm indicates loss
of channel.
For external faults, the reversal of
current at one end shifts the square
waves essentially 180°. As a result,
neither AND-1 nor AND-2 has the
sustained output required to oper-
ate the 4ms timer. No trip occurs at
either line terminal.