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47062 SR5650 Databook 2.00

7-4

Proprietary

VOH/VOL Test

7.4

VOH/VOL Test

7.4.1

Brief Description of a VOH/VOL Tree

The VOH/VOL logic provides signal output on I/O’s when test patterns are applied to the TEST_ODD and TEST_EVEN
pins. A sample of a generic VOH/VOL tree is shown in the figure below.

SB_RX0P/N

AG26/AH26

SB_RX1P/N

AF25/AG25

SB_RX2P/N

AD22/AE22

SB_RX3P/N

AC21/AD21

NC/NC

AE14/AD14

NC/NC

AD13/AC13

NC/NC

AE12/AD12

NC/NC

AD11/AC11

PWM_GPIO1

E16

PWM_GPIO2

B15

PWM_GPIO3

F16

PWM_GPIO4

A15

PWM_GPIO5

C16

PCIE_RESET_GPIO1

B19

PCIE_RESET_GPIO4

E19

PCIE_RESET_GPIO5

E17

DFT_GPIO0

B26

DFT_GPIO1

A25

DFT_GPIO2

B24

DFT_GPIO3

B25

DFT_GPIO4

B23

DFT_GPIO5

A23

DBG_GPIO0

C22

DBG_GPIO1

B22

DBG_GPIO2

B21

DBG_GPIO3

A21

ALLOW_LDTSTOP

D21

LDTSTOP#

E15

No.

Pin Name

Ball Ref.

Содержание SR5650

Страница 1: ...AMD SR5650 Databook Technical Reference Manual Rev 2 00 P N 47062_sr5650_ds_pub 2010 Advanced Micro Devices Inc...

Страница 2: ...ions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights are granted by this publication Except as set forth in AMD s Sta...

Страница 3: ...1 4 1 6 5 Acronyms and Abbreviations 1 4 Chapter 2 Functional Descriptions 2 1 HyperTransport Interface 2 1 2 1 1 Overview 2 1 2 1 2 HyperTransport Flow Control Buffers 2 3 2 2 IOMMU 2 4 2 3 Multiple...

Страница 4: ...nd Pins 3 9 3 10 Strapping Options 3 10 Chapter 4 Timing Specifications 4 1 HyperTransport Bus Timing 4 1 4 2 PCI Express Differential Clock AC Specifications 4 1 4 3 HyperTransport Reference Clock Ti...

Страница 5: ...ree for the SR5650 7 2 7 3 3 XOR Tree Activation 7 2 7 3 4 XOR Tree for the SR5650 7 3 7 4 VOH VOL Test 7 4 7 4 1 Brief Description of a VOH VOL Tree 7 4 7 4 2 VOH VOL Tree Activation 7 5 7 4 3 VOH VO...

Страница 6: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc Table of Contents 4 Proprietary This page is left blank intentionally...

Страница 7: ...nals 2 3 Figure 2 4 Interrupt Routing Paths in Legacy Mode 2 6 Figure 2 5 Interrupt Routing Paths in Legacy Mode with Integrated IOAPIC 2 6 Figure 2 6 Interrupt Routing Path in MSI Mode 2 7 Figure 2 7...

Страница 8: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc List of Figures 2 Proprietary This page is left blank intentionally...

Страница 9: ...trap Definition for STRAP_PCIE_GPP_CFG 3 10 Table 4 1 Timing Requirements for PCIe Differential Clocks GPP1_REFCLK and GPP3_REFCLK at 100MHz 4 1 Table 4 2 Timing Requirements for HyperTransport Refere...

Страница 10: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc List of Tables 2 Proprietary This page intentionally left blank...

Страница 11: ...ATS compliant endpoint devices to cache address translation These features enhance memory protection and support hardware based I O virtualization when combined with appropriate operating system or hy...

Страница 12: ...he SR5650 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM Defect Per Million ratio Full scan implementation on the digital core logic which provides ab...

Страница 13: ...ure 1 2 SR5650 Branding Diagram for A21 Production ASIC Lead Free Part Table 1 1 Device IDs for the SR5690 5670 5650 Chipset Family Device Device ID SR5690 5A10h SR5670 5A12h SR5650 5A13h Northbridge...

Страница 14: ...fers to the bit positions 10 through 15 of the NB_COMMAND register 1 6 4 Hyperlinks Phrases or sentences in blue italic font are hyperlinks to other parts of the manual Users of the PDF version of thi...

Страница 15: ...ort interface IDDQ Direct Drain Quiescent Current IOMMU Input Output Memory Management Unit JTAG Joint Test Access Group An IEEE standard MB Mega Byte NB Northbridge PCI Peripheral Component Interface...

Страница 16: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc 1 6 Proprietary Conventions and Notations This page is left blank intentionally...

Страница 17: ...top processors through sockets F AM3 G34 and C32 The SR5650 supports HyperTransport 3 HT3 as well as HyperTransport 1 HT1 for backward compatibility and for initial boot up For a detailed description...

Страница 18: ...n HyperTransport 3 mode In HyperTransport 1 mode the interface operates by clock forwarding while in HyperTransport 3 mode the interface operates by dynamic phase recovery with frequency information p...

Страница 19: ...bit address extension support 52 bit physical addressing Link disconnection with tristate LS1 and LS2 low power modes Error retry in HyperTransport 3 mode Full HyperTransport defined BIST support for...

Страница 20: ...he strap value to 1 indicating the device to be a primary Northbridge On any secondary SR56x0 the PWM_GPIO5 pin strap must be pulled low In the multi NB mode special PCI Express messages for functions...

Страница 21: ...ll MSI interrupts with address 0xFEEx_xxxx have to be converted to HT interrupts Because of this software is required to program all MSI address registers with an 0xFEEx_xxxx address 2 4 5 Internally...

Страница 22: ...directed to an IOAPIC table entry that is not enabled the IOAPIC sends the INTx message back to the IOC to go to the SB PIC IOAPIC The routing paths are illustrated in Figure 2 5 below Figure 2 5 Int...

Страница 23: ...s All IOMMU cache memories are parity protected When a parity error is detected the access from the associated bank is marked as an automatic miss The cache line is marked as invalid and may later be...

Страница 24: ...nd SYNCFLOODIN The SR5650 may configure the DFT_GPIO0 NMI pin as an input pin for triggering an upstream NMI packet to the processor complex The pin should be driven by a BMC An internal sticky status...

Страница 25: ...100 DBG_GPIO0 SERR_FATAL DBG_GPIO3 NON_FATAL_CORR Attach to a pin that can generate SMI like USB_OC5 IR_TX0 GPM5 DFT_GPIO0 NMI DFT_GPIO5 SYNCFLOODIN Enable only after reset This is a pin strap sampled...

Страница 26: ...or Flow Control Error Surprise Down Error Receiver Error 2 5 5 3 IOMMU Error Reporting The IOMMU specification defines a standard error logging facility that logs error events in system memory with re...

Страница 27: ...e links into the disabled state as an error response in order to help stop data movement within the system Links which received fatal errors may be disabled Also a HyperTransport syncflood event may b...

Страница 28: ...1 states ACPI power management Endpoint and root complex initiated dynamic link degradation Lane reversal Alternative Routing ID Interpretation ARI Access Control Services ACS Advanced Error Reporting...

Страница 29: ...ignment Top View on page 3 2 SR5650 Interface Block Diagram on page 3 4 CPU HyperTransport Interface on page 3 4 PCI Express Interfaces on page 3 5 PCI Express Interface for General Purpose External D...

Страница 30: ...S VDDPCIE VSS L VSS GPP1_TX13N GPP1_TX13P VSS GPP1_RX13N GPP1_RX13P VSS VDDPCIE VDDA18PCIE VSS VSS VDDC M GPP1_TX14N GPP1_TX14P VSS GPP1_RX14N GPP1_RX14P VSS VDDPCIE VSS VSS VSS VDDC VSS N VSS GPP1_TX...

Страница 31: ...TXCTL1N VSS HT_TXCTL0P HT_TXCTL0N P VSS VDDC VSS VSS VDDHT VSS HT_RXCTL1N HT_RXCTL1P VSS HT_RXCTL0N HT_RXCTL0P VSS R VDDC VSS VDDC VSS VSS VDDHT VSS HT_RXCAD15 N HT_RXCAD15 P VSS HT_RXCAD7N HT_RXCAD7P...

Страница 32: ...HT_TXCAD 15 0 P HT_TXCAD 15 0 N O VDDHT VSS Transmitter Command Address and Data Differential Pairs HT_RXCAD 15 0 P HT_RXCAD 15 0 N HT_RXCLK 1 0 P HT_RXCLK 1 0 N HT_RXCTL 1 0 P HT_RXCTL 1 0 N HT_TXCT...

Страница 33: ...Data Differential Pairs Connect to connector s for general purpose external device s on the motherboard GPP1_RX 15 0 P GPP1_RX 15 0 N I VDDA18PCIE VSSA_PCIE 50 between complements General Purpose 1 Re...

Страница 34: ...ential Pair from external clock source GPP1_REFCLKP GPP1_REFCLKN I VDDA18PCIE VSSA_PCIE General Purpose 1 Clock Differential Pair The pair is connected to an external clock generator on the motherboar...

Страница 35: ...or complex Because the pin is used as a pin strap during the power on of the SR5650 an external device must not drive the pin until after SYSRESET is deasserted Also the pin is not 3 3V tolerant and n...

Страница 36: ...VDDHT 1 1V 21 AA22 AB22 AC22 K22 AD23 AE24 AE25 AE26 AE27 AE28 AF27 L21 M22 N21 P22 R21 T22 U21 V22 W21 Y22 HyperTransport Interface digital I O power VDDHTTX 1 2V 11 C24 C25 C26 C27 C28 D22 D23 E22 F...

Страница 37: ...11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH3 AH5 AH7 AH9 B14 B27 B3 C10 C14 C15 C17 C19 C2 C21 C23 C4 C6 C8 D11 D14 D16 D20 D26 D3 D5 D7 D9 E1 E20 E25 E28 E4 F10 F15 F17 F18 F19 F20 F21 F23 F26 F3 F8 G1...

Страница 38: ...is a secondary Northbridge 1 Device is the primary Northbridge Default Reserved PWM_GPIO 4 2 Reserved Make provision for an external pull down resistor on each of the pins but do not install a resist...

Страница 39: ...BS Absolute Period including jitter and spread spectrum modulation 9 847 10 203 ns TCCJITTER Cycle to Cycle Jitter 150 ps Duty Cycle Duty Cycle 40 60 Rise Fall Matching Rising edge rate REFCLK to fall...

Страница 40: ...t 50ps interval 8 VD PK PK is the overall magnitude of the differential signal 9 VD min is the amplitude of the ring back differential measurement guaranteed by design that the ring back will not cros...

Страница 41: ...nts specified in the SR5690 Motherboard Design Guide Table 4 5 SR5650 Power Rail Power up Sequence Symbol Parameter Requirement Comment T10 1 8V rails to VDDHTTX 1 2V VDDHTTX ramps after 1 8V rails Se...

Страница 42: ...Proprietary Power Rail Sequence 4 5 2 Power Down For power down the rails should either be turned off simultaneously or in the reversed order of the power up sequence Variations in speeds of decay du...

Страница 43: ...18HTPLL 1 8 1 746 1 854 1 71 1 89 V HyperTransport interface 1 8V PLL power Note The voltage set point must be contained within the DC specification in order to ensure proper operation Voltage ripple...

Страница 44: ...g Case Temperature 0 95 C 1 Absolute Rated Junction Temperature 115 C 2 Storage Temperature 40 60 C Ambient Temperature 0 55 C 3 Thermal Design Power 12 6 W 4 Notes 1 The maximum operating case temper...

Страница 45: ...two base to emitter voltage readings one using current I and the other using current N x I N Ratio of the two thermal diode currents 10 when using an ADI thermal sensor e g ADM 1020 1030 Ideality fac...

Страница 46: ...5 3 shows the detailed ball arrangement for the SR5650 Figure 5 2 SR5650 692 Pin FCBGA Package Outline Table 5 6 SR5650 692 Pin FCBGA Package Physical Dimensions Ref Min mm Typical mm Max mm c 0 56 0...

Страница 47: ...exceed 6 lbf Note that a total load of 4 6 lbf is adequate to secure the thermal management device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interfa...

Страница 48: ...chemistry of flux used in the SMT process Modifications to the reference reflow profile may be required in order to accommodate the requirements of the other components in the application An oven wit...

Страница 49: ...lder SAC305 405 Tin Silver Copper Reflow Profile 50 250 150 200 100 Soldering Zone 45 90 sec Max 60 80 sec typical Peak Temp 235 o C 5 typ 245 o C max 220 deg C 60 80 sec typical 2 0o C Sec 2 0o C Sec...

Страница 50: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc 5 8 Proprietary Package Information This page is left blank intentionally...

Страница 51: ...me and contributes minimum power savings S0 C2 Stop Grant Caches Snoopable Stop Grant or Cache Snoopable CPU state This state offers more power savings but has a higher latency on resume than the C1 s...

Страница 52: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc 6 2 Proprietary ACPI Power Management Implementation This page intentionally left blank...

Страница 53: ...de which is not entirely compliant to the IEEE 1149 1 standard in order to allow board level testing of neighboring devices An XOR TREE test mode on all the digital I O s to allow for proper soldering...

Страница 54: ...ls in the tree A toggle of any of these balls in the XOR tree will cause the output to toggle 7 3 3 XOR Tree Activation To activate the XOR tree and run a XOR test perform the sequence below 1 Supply...

Страница 55: ...26 3 HT_RXCAD2P N AB28 AB27 4 HT_RXCAD3P N AA27 AA26 5 HT_RXCAD4P N W27 W26 6 HT_RXCAD5P N V28 V27 7 HT_RXCAD6P N U27 U26 8 HT_RXCAD7P N T28 T27 9 HT_RXCTL0P N R27 R26 10 HT_RXCAD8P N AD25 AD24 11 HT_...

Страница 56: ...AG26 AH26 58 SB_RX1P N AF25 AG25 59 SB_RX2P N AD22 AE22 60 SB_RX3P N AC21 AD21 61 NC NC AE14 AD14 62 NC NC AD13 AC13 63 NC NC AE12 AD12 64 NC NC AD11 AC11 65 PWM_GPIO1 E16 66 PWM_GPIO2 B15 67 PWM_GPI...

Страница 57: ...GPP1_REFCLKP N and GPP3_REFCLKP N pins 2 Set POWERGOOD to 0 3 Set TESTMODE to 1 4 Set PCIE_RESET_GPIO2 to 0 5 Wait 5 or more I2C_CLK cycles 6 Load JTAG instruction register with the instruction 0001 1...

Страница 58: ...Odd 11 HT_TXCAD9P N F24 F25 Even 12 HT_TXCAD10P N G23 G24 Odd 13 HT_TXCAD11P N H24 H25 Even 14 HT_TXCAD12P N K24 K25 Odd 15 HT_TXCAD13P N L23 L24 Even 16 HT_TXCAD14P N M24 M25 Odd 17 HT_TXCAD15P N N2...

Страница 59: ...5 PWM_GPIO1 E16 Even 66 PWM_GPIO2 B15 Odd 67 PWM_GPIO5 C16 Even 68 PCIE_RESET_GPIO1 B19 Odd 69 PCIE_RESET_GPIO4 E19 Even 70 PCIE_RESET_GPIO5 E17 Odd 71 DFT_GPIO0 B26 Even 72 DFT_GPIO1 A25 Odd 73 DFT_G...

Страница 60: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc 7 8 Proprietary VOH VOL Test This page intentionally left blank...

Страница 61: ...A 1 Appendix A Pin Listings This appendix contains pin listings for the SR5650 sorted in different ways To go to the listing of interest use the linked cross references below SR5650 Pin Listing Sorted...

Страница 62: ...GPP3_REFCLKP AA16 VDDPCIE AA17 VSS AA18 VDDPCIE AA19 VSS AA2 NC AA20 VSS AA21 THERMALDIODE_N AA22 VDDHT AA23 HT_RXCAD11N AA24 HT_RXCAD11P AA25 VSS AA26 HT_RXCAD3N AA27 HT_RXCAD3P AA28 VSS AA3 NC AA4...

Страница 63: ...NC AE15 VSS AE16 GPP3_RX4P AE17 VSS AE18 GPP3_RX2P AE19 VSS AE2 NC AE20 PCE_BCALRP AE21 VSS AE22 SB_RX2N AE23 VSS AE24 VDDHT AE25 VDDHT AE26 VDDHT AE27 VDDHT AE28 VDDHT AE3 NC AE4 VDDPCIE AE5 VSS AE6...

Страница 64: ...22 DBG_GPIO1 B23 DFT_GPIO4 B24 DFT_GPIO2 B25 DFT_GPIO3 B26 DFT_GPIO0 NMI B27 VSS B3 VSS B4 GPP1_TX6N B5 GPP1_RX6P B6 GPP1_TX5N B7 GPP1_TX4P B8 GPP1_TX3N B9 GPP1_TX2P C1 VDDPCIE C10 VSS C11 GPP1_TX0N C...

Страница 65: ...8PCIE F14 PCE_TCALRP F15 VSS F16 PWM_GPIO3 F17 VSS F18 VSS F19 VSS F2 GPP1_TX8P F20 VSS F21 VSS F22 VDDHTTX F23 VSS F24 HT_TXCAD9P F25 HT_TXCAD9N F26 VSS F27 HT_TXCAD1P F28 HT_TXCAD1N F3 VSS F4 GPP1_R...

Страница 66: ...GPP1_RX12N K5 GPP1_RX12P K6 VSS K7 VDDPCIE K8 VSS L1 VSS L11 VDDA18PCIE L12 VSS L13 VSS L14 VDDC L15 VSS L16 VDDC L17 VSS L18 VSS L2 GPP1_TX13N L21 VDDHT L22 VSS L23 HT_TXCAD13P L24 HT_TXCAD13N L25 V...

Страница 67: ...SS R18 VSS R2 NC R21 VDDHT R22 VSS R23 HT_RXCTL1N R24 HT_RXCTL1P R25 VSS R26 HT_RXCTL0N R27 HT_RXCTL0P R28 VSS R3 NC R4 VSS R5 NC R6 NC R7 VSS R8 VDDPCIE T1 NC T11 VSS T12 VSS T13 VDDC T14 VSS T15 VDD...

Страница 68: ...VSS V27 HT_RXCAD5N V28 HT_RXCAD5P V3 VSS V4 NC V5 NC V6 VSS V7 VDDPCIE V8 NC W1 VSS W2 NC W21 VDDHT W22 VSS W23 HT_RXCAD12N W24 HT_RXCAD12P W25 VSS W26 HT_RXCAD4N W27 HT_RXCAD4P W28 VSS W3 NC W4 VSS W...

Страница 69: ...N C5 GPP1_RX6P B5 GPP1_RX7N D1 GPP1_RX7P D2 GPP1_RX8N F4 GPP1_RX8P F5 GPP1_RX9N G5 GPP1_RX9P G6 GPP1_TX0N C11 GPP1_TX0P B11 GPP1_TX10N H1 GPP1_TX10P H2 GPP1_TX11N J2 GPP1_TX11P J3 GPP1_TX12N K1 GPP1_T...

Страница 70: ...8 HT_RXCLK1N Y24 HT_RXCLK1P Y25 HT_RXCTL0N R26 HT_RXCTL0P R27 HT_RXCTL1N R23 HT_RXCTL1P R24 HT_TXCAD0N E27 HT_TXCAD0P E26 HT_TXCAD10N G24 HT_TXCAD10P G23 HT_TXCAD11N H25 HT_TXCAD11P H24 HT_TXCAD12N K2...

Страница 71: ...W2 NC W3 NC W5 NC W6 NC Y1 NC Y2 NC Y4 NC Y5 OSCIN B17 PCE_BCALRN AD20 PCE_BCALRP AE20 PCE_RCALRN AD10 PCE_RCALRP AE10 PCE_TCALRN E14 PCE_TCALRP F14 PCIE_RESET_GPIO1 B19 PCIE_RESET_GPIO2 D17 Ball Nam...

Страница 72: ...DC U14 VDDC U16 VDDHT AA22 VDDHT AB22 VDDHT AC22 VDDHT AD23 VDDHT AE24 VDDHT AE25 VDDHT AE26 VDDHT AE27 VDDHT AE28 VDDHT AF27 VDDHT K22 VDDHT L21 VDDHT M22 VDDHT N21 VDDHT P22 VDDHT R21 VDDHT T22 VDDH...

Страница 73: ...Name Ball VSS AB8 VSS AC1 VSS AC10 VSS AC12 VSS AC14 VSS AC16 VSS AC18 VSS AC20 VSS AC25 VSS AC28 VSS AC4 VSS AC5 VSS AC8 VSS AD26 VSS AD3 VSS AD4 VSS AE1 VSS AE11 VSS AE13 VSS AE15 VSS AE17 VSS AE19...

Страница 74: ...16 Ball Name Ball VSS H17 VSS H18 VSS H19 VSS H20 VSS H21 VSS H23 VSS H26 VSS H3 VSS H6 VSS J1 VSS J22 VSS J25 VSS J28 VSS J4 VSS J7 VSS K23 VSS K26 VSS K3 VSS K6 VSS K8 VSS L1 VSS L12 VSS L13 VSS L15...

Страница 75: ...VSS T12 VSS T14 VSS T16 VSS T18 VSS T21 VSS T23 VSS T26 VSS T3 VSS T6 VSS T8 VSS U1 VSS U11 VSS U12 VSS U13 VSS U15 VSS U17 VSS U18 VSS U22 VSS U25 VSS U28 VSS U4 VSS U7 VSS V12 VSS V13 VSS V14 VSS V1...

Страница 76: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc Appendix A 16 Proprietary SR5650 Pin Listing Sorted by Ball Reference This page is left blank intentionally...

Страница 77: ...2010 Advanced Micro Devices Inc 47062 SR5650 Databook 2 00 Proprietary Appendix B 1 Appendix B Revision History Rev 2 00 Dec 2010 First release of the public version...

Страница 78: ...47062 SR5650 Databook 2 00 2010 Advanced Micro Devices Inc Appendix B 2 Proprietary This page intentionally left blank...

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