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6

Interface Signals

Chapter 2

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

31994A —1 August 2004

2.3

Push-Pull (PP) Drivers

The AMD Sempron processor model 10 supports push-pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.

See “ZN and ZP Pins” on page 75 for more information.

2.4

AMD Athlon™ System Bus Signals

The AMD Athlon system bus is a clock-forwarded, point-to-
point interface with the following three point-to-point channels:

■

A 13-bit unidirectional output address/command channel

■

A 13-bit unidirectional input address/command channel

■

A 72-bit bidirectional data channel

Fo r m o r e i n f o r m a t i o n , s e e C h a p t e r 6 , “ 3 3 3 F S B
AMD Sempron™ Processor Model 10 with 256K L2 Cache
Specifications” on page 21, Chapter 7, “Electrical Data” on
page 25, and the

AMD Athlon™ and AMD Duron™ System Bus

Specification

, order# 21902.

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Содержание Sempron 10

Страница 1: ...AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Publication 31994 Rev A 1 Issue Date August 2004 TM...

Страница 2: ...ifications and prod uct descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication E...

Страница 3: ...tocol 12 Connect State Diagram 16 4 3 Clock Control 18 5 CPUID Support 19 6 333 FSB AMD Sempron Processor Model 10 with 256K L2 Cache Specifications 21 6 1 Electrical and Thermal Specifications for th...

Страница 4: ...Requirements 42 Northbridge Reset Pins 42 9 Mechanical Data 43 9 1 Die Loading 43 9 2 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Dimensions 44 9 3 AMD Sempron Processor Model 10 Pa...

Страница 5: ...TPCLK Pin 73 SYSCLK and SYSCLK 73 THERMDA and THERMDC Pins 73 VCCA Pin 73 VID 4 0 Pins 74 VREFSYS Pin 74 ZN and ZP Pins 75 11 Ordering Information 77 Standard AMD Sempron Processor Model 10 Products 7...

Страница 6: ...vi Table of Contents AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 7: ...igure 7 Processor Connect State Diagram 17 Figure 8 SYSCLK Waveform 22 Figure 9 VCC_CORE Voltage Waveform 29 Figure 10 SYSCLK and SYSCLK Differential Clock Signals 31 Figure 11 General ATE Open Drain...

Страница 8: ...viii List of Figures AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 9: ...Characteristics 31 Table 12 General AC and DC Characteristics 32 Table 13 Thermal Diode Electrical Characteristics 35 Table 14 Guidelines for Platform Thermal Protection of the Processor 37 Table 15...

Страница 10: ...x List of Tables AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 11: ...istory xi 31994A 1August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Revision History Date Rev Description August 2004 A 1 Initial release of the AMD Sempron Processor Model 10 D...

Страница 12: ...xii Revision History AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 13: ...ssor The 4 digit model numbering system helps identify overall software performance the higher the number the better the performance Detailed technical documentation and performance benchmarks are ava...

Страница 14: ...ocessor model 10 with 256K of L2 cache features a seventh generation microarchitecture with an integrated exclusive L2 cache which supports the growing processor and system bandwidth requirements of e...

Страница 15: ...rmance on high end software applications utilizing high bandwidth system capabilities Advanced two level translation look aside buffer TLB structures for both enhanced data and instruction address tra...

Страница 16: ...Figure 1 Typical AMD Sempron Processor Model 10 System Block Diagram SDRAM or DDR AGP Bus Memory Bus AGP PCI Bus LAN SCSI LPC Bus USB Dual EIDE AMD Sempron Proces sor Model 10 System Controller North...

Страница 17: ...e controlled push pull low voltage swing signaling technology contained within the Socket A socket For more information see AMD Athlon System Bus Signals on page 6 Chapter 10 Pin Descriptions on page...

Страница 18: ...onnected to the ZN and ZP pins See ZN and ZP Pins on page 75 for more information 2 4 AMD Athlon System Bus Signals The AMD Athlon system bus is a clock forwarded point to point interface with the fol...

Страница 19: ...ram SDATA 63 0 SDATAINCLK 3 0 SDATAOUTCLK 3 0 Data SADDIN 14 2 SADDINCLK Probe SysCMD SADDOUT 14 2 SADDOUTCLK VID 4 0 FID 3 0 A20M CLKFWDRST CONNECT COREFB COREFB FERR IGNNE INIT INTR NMI PROCRDY PWRO...

Страница 20: ...8 Logic Symbol Diagram Chapter 3 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 21: ...ement states of the processor The figure includes the ACPI Cx naming convention for these states Figure 3 AMD Sempron Processor Model 10 Power Management States C1 Halt C0 Working4 Execute HLT SMI INT...

Страница 22: ...initiate a system bus connect if it is disconnected then issue a Stop Grant special cycle When STPCLK is deasserted the processor will exit the Stop Grant state and re enter the Halt state The process...

Страница 23: ...ognized If RESET is sampled asserted during the Stop Grant state the processor exits the Stop Grant state and the reset process begins There are two mechanisms for asserting STPCLK hardware and softwa...

Страница 24: ...r returns to the same state as when it entered the Probe state Halt or Stop Grant state When probe activity is completed the processor only returns to a low power state after the Northbridge disconnec...

Страница 25: ...top Grant special cycle to the PCI bus or passing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransport technology This note applies to curren...

Страница 26: ...nt state 2 When the processor recognizes STPCLK asserted it enters the Stop Grant state and then issues a Stop Grant special cycle 3 When the special cycle is received by the Northbridge it deasserts...

Страница 27: ...e of events removes the processor from the Stop Grant state and connects it to the system bus 1 The Southbridge deasserts STPCLK informing the processor of a wake event 2 When the processor recognizes...

Страница 28: ...ending 2 A disconnect is requested and no probes are pending 3 A Connect special cycle from the processor 4 No probes are pending 5 PROCRDY is deasserted 6 A probe needs service 7 PROCRDY is asserted...

Страница 29: ...T is deasserted by the Northbridge 6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted Action A CLKFWDRST is asserted by the Northbridge B Issue a Connect special cycle C Return...

Страница 30: ...ock Control The processor implements a Clock Control CLK_Ctl MSR address C001_001Bh that determines the internal clock divisor when the AMD Athlon system bus is disconnected Refer to the AMD Athlon an...

Страница 31: ...performed through the use of the CPUID instruction that provides complete information about the processor vendor type name etc and its capabilities Software can make use of this information to accurat...

Страница 32: ...20 CPUID Support Chapter 5 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 33: ...0 C 2000 2800 Notes 1 See Figure 3 AMD Sempron Processor Model 10 Power Management States on page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the...

Страница 34: ...Low Time 1 0 ns t4 Fall Time 2 ns t5 Rise Time 2 ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon system bus clock...

Страница 35: ...Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input clocks 4 25 pF COUT Capacitance on output clocks 4 12 pF Sync TVAL RSTCLK to Output Valid 800 2000 ps 4 5 TSU Setup to RS...

Страница 36: ...100 A IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN VREF Nominal 100 A VIH Input High Voltage VREF 200 VCC_CORE 500 mV VIL Input Low Voltage 500 VREF 200 mV ILEAK_P Tristate Leakage Pullup VIN VSS...

Страница 37: ...page 26 VID 4 0 Pins on page 74 VCCA AC and DC Characteristics on page 27 VCC_CORE Characteristics on page 28 VCCA Pin on page 73 and COREFB and COREFB Pins on page 69 Frequency FID 3 0 See Frequency...

Страница 38: ...NCLK1 SCANCLK2 SCANSHIFTEN SCANINTEVAL ANALOG See General AC and DC Characteristics on page 32 PLL Bypass and Test Pins on page 72 Scan Pins on page 73 Analog Pin on page 68 Miscellaneous DBREQ DBRDY...

Страница 39: ...Characteristics Parameter Description Min Max IOL Output Current Low 6 mA VOH Output High Voltage 2 625 V 1 VOH VCC_CORE 1 60 V 2 Note 1 The FID pins must not be pulled above 2 625 V which is equal t...

Страница 40: ...C Characteristics Symbol Parameter Limit in Working State Units VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM 50 mV VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM 50 mV VCC_CORE...

Страница 41: ...veform response to perturbation The tMIN_AC negative AC transient excursion time and tMAX_AC positive AC transient excursion time represent the maximum allowable time below or above the DC tolerance t...

Страница 42: ...can adversely affect long term reliability or result in functional damage Table 10 lists the maximum absolute ratings of operation for the AMD Sempron processor model 10 Table 10 Absolute Ratings Para...

Страница 43: ...LK and SYSCLK signals Figure 10 SYSCLK and SYSCLK Differential Clock Signals Table 11 SYSCLK and SYSCLK DC Characteristics Symbol Description Min Max Units VThreshold DC Crossing before transition is...

Страница 44: ...between VCC_CORE minimum and VCC_CORE maximum 3 IOL and IOH are measured at VOL maximum and VOH minimum respectively 4 Synchronous inputs outputs are specified with respect to RSTCLK and RSTCK at the...

Страница 45: ...imum and VOH minimum respectively 4 Synchronous inputs outputs are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which input...

Страница 46: ...omated test equipment ATE to test for validity on open drain pins Refer to Table 12 General AC and DC Characteristics on page 32 for timing requirements Figure 11 General ATE Open Drain Test Circuit O...

Страница 47: ...information about calculations for the ideal diode equation and temperature offset correction see Appendix A Thermal Diode Calculations on page 77 Table 13 Thermal Diode Electrical Characteristics Sym...

Страница 48: ...e over temperature condition to processor shutdown to prevent thermal damage to the processor Systems that do not implement thermal protection circuitry or that do not react within the time specified...

Страница 49: ...ing die temperature of the processor The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event Refer...

Страница 50: ...ble 15 APIC Pin AC and DC Characteristics continued Symbol Parameter Description Condition Min Max Units Notes Notes 1 Characterized across DC supply voltage range 2 The 2 625 V value is equal to 2 5...

Страница 51: ...Description Figure 12 shows the relationship between key signals in the system during a power up sequence This figure details the requirements of the processor Figure 12 Signal Relationship Requireme...

Страница 52: ...ds from the 3 3 V supply being within specification This delay ensures that the system clock SYSCLK SYSCLK is operating within specification when PWROK is asserted The processor core voltage VCC_CORE...

Страница 53: ...t the timing requirements as defined in Table 12 General AC and DC Characteristics on page 32 The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWR...

Страница 54: ...code The SIP is sent to the processor using the SIP protocol This protocol uses the PROCRDY CONNECT and CLKFWDRST signals that are synchronous to SYSCLK For more information about FID 3 0 see FID 3 0...

Страница 55: ...the die to an approved heat sink Any heat sink design should avoid loads on corners and edges of die The OPGA package has compliant pads that serve to bring surfaces in planar contact Tool assisted z...

Страница 56: ...l Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 E9 1 66 1 96 D1 E1 45 72 BSC G H 4 50 D2 7 42 REF A 1 942 REF D3 3 30 3 60 A1 1 00 1 20 D...

Страница 57: ...Chapter 9 Mechanical Data 45 31994A 1August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Figure 13 AMD Sempron Processor Model 10 Part Number 27488 OPGA Package Diagram...

Страница 58: ...r Symbol Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 G H 4 50 D1 E1 45 72 BSC A 1 917 REF D2 7 42 REF A1 0 977 1 177 D3 3 30 3 60 A2 0...

Страница 59: ...Chapter 9 Mechanical Data 47 31994A 1August 2004 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Figure 14 AMD Sempron Processor Model 10 Part Number 27493 OPGA Package Diagram...

Страница 60: ...48 Mechanical Data Chapter 9 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 61: ...ions and a cross referenced listing of pin locations to signal names 10 1 Pin Diagram and Pin Name Abbreviations Figure 15 on page 50 shows the staggered Pin Grid Array PGA for the AMD Sempron process...

Страница 62: ...C VSS VSS VSS VSS R S SCNCK1 SCNINV SCNCK2 THDA NC SD 7 SD 15 SD 6 S T VSS VSS VSS VSS VCC VCC VCC VCC T U TDI TRST TDO THDC NC SD 5 SD 4 NC U V VCC VCC VCC VCC VSS VSS VSS VSS V W FID 0 FID 1 VREF_S...

Страница 63: ...EY NC CLKIN CLKIN 17 18 VSS VSS VSS VSS VCC VCC VCC VCC 18 19 NC SD 59 SD 58 NC NC NC RCLK RCLK 19 20 VCC VCC VCC VCC VSS VSS VSS VSS 20 21 SD 57 SD 56 SD 36 NC NC CLKFR K7CO K7CO 21 22 VSS VSS VSS VS...

Страница 64: ...G1 FID 0 W1 FID 1 W3 FID 2 Y1 FID 3 Y3 FLUSH AL3 FSB0 FSB_Sense 0 AG31 FSB1 FSB_Sense 1 AH30 IGNNE AJ1 INIT AJ3 INTR AL1 K7CO K7CLKOUT AL21 K7CO K7CLKOUT AN21 KEY G7 KEY G9 KEY G15 KEY G17 KEY G23 KEY...

Страница 65: ...Abbreviations continued Abbreviation Full Name Pin NC AJ19 NC AJ27 NC AK8 NC AL7 NC AL9 NC AL11 NC AL25 NC AL27 NC AM8 NC AN7 NC AN9 NC AN11 NC AN25 NC AN27 NMI AN3 PICCLK N1 PICD 0 PICD 0 N3 PICD 1...

Страница 66: ...SCANCLK2 S5 SCNINV SCANINTEVAL S3 SCNSN SCANSHIFTEN Q5 SD 0 SDATA 0 AA35 SD 1 SDATA 1 W37 SD 2 SDATA 2 W35 Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin SD 3 SDATA 3 Y35 SD 4 SD...

Страница 67: ...CLK 0 W33 SDIC 1 SDATAINCLK 1 J35 SDIC 2 SDATAINCLK 2 E27 SDIC 3 SDATAINCLK 3 E15 SDINV SDATAINVALID AN33 SDOC 0 SDATAOUTCLK 0 AE35 SDOC 1 SDATAOUTCLK 1 C37 Table 19 Pin Name Abbreviations continued A...

Страница 68: ...ORE T36 VCC VCC_CORE V2 VCC VCC_CORE V4 VCC VCC_CORE V6 VCC VCC_CORE V8 Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin VCC VCC_CORE X30 VCC VCC_CORE X32 VCC VCC_CORE X34 VCC VCC_...

Страница 69: ...23 VID 0 L1 VID 1 L3 VID 2 L5 VID 3 L7 VID 4 J7 VREF_S VREF_SYS W5 VSS B2 VSS B6 VSS B10 VSS B14 VSS B18 VSS B22 VSS B26 VSS B30 VSS B34 VSS D6 VSS D10 VSS D14 VSS D18 Table 19 Pin Name Abbreviations...

Страница 70: ...SS AB4 VSS AB6 VSS AD32 VSS AD34 VSS AD36 VSS AF2 VSS AF4 VSS AF12 VSS AF16 Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin VSS AH12 VSS AH16 VSS AH20 VSS AH24 VSS AH28 VSS AH32 V...

Страница 71: ...sh pull mode driven by a single source O indicates open drain mode that allows devices to share the pin Note The AMD Sempron processor supports push pull drivers For more information see Push Pull PP...

Страница 72: ...P A35 SDATA 40 P B G A37 SDATA 30 P B P B2 VSS B4 VCC_CORE B6 VSS B8 VCC_CORE B10 VSS B12 VCC_CORE B14 VSS B16 VCC_CORE B18 VSS B20 VCC_CORE B22 VSS B24 VCC_CORE B26 VSS B28 VCC_CORE B30 VSS B32 VCC_C...

Страница 73: ...ATA 46 P B P E25 NC Pin page 72 E27 SDATAINCLK 2 P I G E29 SDATA 33 P B P E31 SDATA 32 P B P Table 20 Cross Reference by Pin Location Pin Name Description L P R E33 NC Pin page 72 E35 SDATA 31 P B P E...

Страница 74: ...page 72 H32 NC Pin page 72 H34 VSS H36 VSS J1 SADDOUT 0 page 73 P O J3 SADDOUT 1 page 73 P O Table 20 Cross Reference by Pin Location Pin Name Description L P R J5 NC Pin page 72 J7 VID 4 page 74 O O...

Страница 75: ...Q37 SDATA 16 P B G R2 VCC_CORE R4 VCC_CORE R6 VCC_CORE R8 VCC_CORE R30 VSS R32 VSS Table 20 Cross Reference by Pin Location Pin Name Description L P R R34 VSS R36 VSS S1 SCANCLK1 page 73 P I S3 SCANI...

Страница 76: ...ge 72 Y33 NC Pin page 72 Y35 SDATA 3 P B G Y37 SDATA 12 P B P Z2 VCC_CORE Z4 VCC_CORE Table 20 Cross Reference by Pin Location Pin Name Description L P R Z6 VCC_CORE Z8 VCC_CORE Z30 VSS Z32 VSS Z34 VS...

Страница 77: ...28 NC Pin page 72 Table 20 Cross Reference by Pin Location Pin Name Description L P R AF30 NC Pin page 72 AF32 NC Pin page 72 AF34 VCC_CORE AF36 VCC_CORE AG1 FERR page 69 P O AG3 RESET I AG5 NC Pin pa...

Страница 78: ...N 0 page 73 P I AJ31 SFILLVALID P I G AJ33 SADDINCLK P I G AJ35 SADDIN 6 P I P AJ37 SADDIN 3 P I G Table 20 Cross Reference by Pin Location Pin Name Description L P R AK2 VSS AK4 VSS AK6 CPU_PRESENCE...

Страница 79: ...VCC_CORE AM28 VSS AM30 VCC_CORE Table 20 Cross Reference by Pin Location Pin Name Description L P R AM32 VSS AM34 VCC_CORE AM36 VSS AN1 No Pin page 72 AN3 NMI P I AN5 SMI P I AN7 NC Pin page 72 AN9 NC...

Страница 80: ...uron System Bus Specification order 21902 for information about the system bus pins PROCRDY PWROK RESET SADDIN 14 2 SADDINCLK SADDOUT 14 2 SADDOUTCLK SDATA 63 0 SDATAINCLK 3 0 SDATAINVALID SDATAOUTCLK...

Страница 81: ...de processor core voltage feedback to the system CPU_PRESENCE Pin CPU_PRESENCE is connected to VSS on the processor package If pulled up on the motherboard CPU_PRESENCE may be used to detect the prese...

Страница 82: ...about Serialization Initialization Packets and SIP protocol The processor FID 3 0 outputs are open drain and 2 5 V tolerant To prevent damage to the processor do not pull these Table 21 FID 3 0 Clock...

Страница 83: ...nt side bus FSB setting of this processor Proper detection of the FSB setting requires the implementation of a pull up resistor on the motherboard Refer to the AMD Athlon Processor Based Motherboard D...

Страница 84: ...igners should treat key pins like NC No Connect pins A socket designer has the option of creating a top mold piece that allows PGA key pins only where designated However sockets that populate all 16 k...

Страница 85: ...bled with pulldown resistors to ground on the motherboard SMI Pin SMI is an input that causes the processor to enter the system management mode STPCLK Pin STPCLK is an input that causes the processor...

Страница 86: ...ide order 24363 VREFSYS Pin VREFSYS W5 drives the threshold voltage for the system bus input receivers The value of VREFSYS is system specific In addition to minimize VCC_CORE noise rejection from VRE...

Страница 87: ...ZP AE5 are the push pull compensation circuit pins In Push Pull mode selected by the SIP parameter SysPushPull asserted ZN is tied to VCC_CORE with a resistor that has a resistance matching the impeda...

Страница 88: ...76 Pin Descriptions Chapter 10 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 89: ...Example for the AMD Sempron Processor Model 10 with 256K L2 Cache D U T 3 OPN1 Advanced Front Side Bus D 333 Size of L2 Cache 3 256 Kbytes Die Temperature T 90 C Operating Voltage U 1 60 V Package Typ...

Страница 90: ...78 Ordering Information Chapter 11 AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 91: ...al information about this thermal diode see Table 13 Thermal Diode Electrical Characteristics on page 35 Ideal Diode Equation The ideal diode equation uses the variables and constants defined in Table...

Страница 92: ...orrection A temperature offset may be required to correct the value measured by a temperature sensor An offset is necessary if a difference exists between the lumped ideality factor of the processor a...

Страница 93: ...further details Equation 3 shows the equation for calculating the lumped ideality factor nf lumped in sensors that do not employ series resistance cancellation Equation 4 shows the equation for calcul...

Страница 94: ...82 Appendix A Thermal Diode Calculations AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

Страница 95: ...owest signal numbers are contained in brackets and separated by a colon for example D 63 0 Reserved Bits and Signals Signals or bus bits marked reserved must be driven inactive or left unconnected as...

Страница 96: ...nificant byte position little end In byte diagrams bit positions are numbered from right to left the little end is on the right and the big end is on the left Data structure diagrams in memory show lo...

Страница 97: ...d in this document Table 26 Abbreviations Abbreviation Meaning A Ampere F Farad G Giga Gbit Gigabit Gbyte Gigabyte H Henry h Hexadecimal K Kilo Kbyte Kilobyte M Mega Mbit Megabit Mbyte Megabyte MHz Me...

Страница 98: ...ammable Interrupt Controller BIOS Basic Input Output System BIST Built In Self Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Array DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Me...

Страница 99: ...ctory Entry PDT Page Directory Table PGA Pin Grid Array PLL Phase Locked Loop PMSM Power Management State Machine POS Power On Suspend POST Power On Self Test RAM Random Access Memory ROM Read Only Me...

Страница 100: ...empron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004 VAS Virtual Address Space VPA Virtual Page Address VGA Video Graphics Adapter USB Universal Serial Bus ZDB Zero Delay Buffer...

Страница 101: ...b site http www amd com AMD Athlon Processor x86 Code Optimization Guide order 22007 AMD Processor Recognition Application Note order 20734 Methodologies for Measuring Temperature on AMD Athlon and AM...

Страница 102: ...90 Appendix B Conventions and Abbreviations AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 31994A 1August 2004...

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