AMD Elan SC520, Руководство пользователя

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Pin Information
2-6 Élan™SC520 Microcontroller User’s Manual
ROM/Flash Controller
BOOTCS — O ROM/Flash Boot Chip Select is an active Low output that provides
the chip select for the startup ROM and/or the ROM/Flash array
(BIOS, HAL, O/S, etc.). The BOOTCS signal asserts for accesses
made to the 64-Kbyte segment that contains the Am5
x
86 CPU boot
vector: addresses 3FF0000h–3FFFFFFh. In addition to this linear
decode region, BOOTCS asserts in response to accesses to user-
programmable address regions.
FLASHWR — O Flash Write indicates that the current cycle is a write of the selected
Flash device. When this signal is asserted, the selected Flash device
can latch data from the data bus.
GPA25–GPA0 — O General-Purpose Address Bus provides the address to the system’s
ROM/Flash devices. It is also the address bus for the GP bus devices.
Twenty-six address lines provide a maximum addressable space of 64
Mbytes for each ROM chip select.
GPD15–GPD0 — B General-Purpose Data Bus inputs data during memory and I/O read
cycles and outputs data during memory and I/O write cycles.
A reset configuration pin (CFG2) allows the GP bus to be used for the
boot chip-select ROM interface. Configuration registers are used to
select whether ROMCS2 and ROMCS1 use the GP bus data bus or
the MD data bus. The GP data bus supports 16-bit or 8-bit ROM
interfaces. Two data buses are selectable to facilitate the use of ROM
in a mixed voltage system.
MD31–MD0 — B Memory Data Bus inputs data during SDRAM read cycles and
outputs data during SDRAM write cycles. Configuration registers are
used to select whether ROMCS2 and ROMCS1 use the GP bus data
bus or the MD data bus. A reset configuration pin (CFG2) allows the
GP data bus to be used for BOOTCS. The memory data bus supports
an 8-, 16-, or 32-bit ROM interface.
ROMBUFOE — O ROM Buffer Output Enable is an optional signal used to enable a
buffer to the ROM/Flash devices if they need to be isolated from the
ÉlanSC520 microcontroller, other GP bus devices, or SDRAM system
for voltage or loading considerations. This signal asserts for all
accesses through the ROM controller. The buffer direction is controlled
by the ROMRD or FLASHWR signal.
ROMCS2 [GPCS2] O ROM/Flash Chip Selects are signals that can be programmed to be
asserted for accesses to user-programmable address regions.
ROMCS1 [GPCS1] O
ROMRD — O ROM/Flash Read indicates that the current cycle is a read of the
selected ROM/Flash device. When this signal is asserted, the selected
ROM device can drive data onto the data bus.
Peripheral Component Interconnect (PCI) Bus
AD31–AD0 — B PCI Address Data Bus is the PCI time-multiplexed address/data bus.
CBE3–CBE0 — B Command or Byte-Enable Bus functions 1) as a time-multiplexed
bus command that defines the type of transaction on the AD bus,
or 2) as byte enables:
CBE0 for AD7–AD0
CBE1 for AD15–AD8
CBE2 for AD23–AD16
CBE3 for AD31–AD24
CLKPCIIN — I PCI Bus Clock Input is the 33-MHz PCI bus clock. This pin can be
connected to the CLKPCIOUT pin for systems where the ÉlanSC520
microcontroller is the source of the PCI bus clock.
Table 2-2 Signal Descriptions (Continued)
Signal
Multiplexed
Signal Type Description