AMD Elan SC520, Руководство пользователя

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Write Buffer and Read Buffer
11-12 Élan™SC520 Microcontroller User’s Manual
In a system configured with multiple active DMA channels, read buffer misses will most
likely occur for each change of channel tenure. This is because each DMA channel
accesses different SDRAM regions that will most likely miss the read buffer, which still
contains the cache line of data fetched during the previous channel’s tenure. Therefore, it
would be ideal for as many transfers to occur as possible while a particular DMA channel
has access to SDRAM to utilize the rest of the cache line fetched during the DMA transfer’s
first doubleword request. This implies that, in a system with many active DMA channels
configured for single transfer mode, read buffer misses will occur that do not utilize the
cache line of data fetched during the previous channels tenure.
Demand and block DMA transfer modes will most likely take advantage of the rest of the
cache-line fetches, since devices that use these modes typically have longer bus tenure,
resulting in a higher utilization of the fetched data.
11.5.4 PCI Considerations
As a PCI target, the ÉlanSC520 microcontroller can respond to PCI master write and read
requests to SDRAM. To facilitate large burst transfers as a PCI target, a 64-level write data
FIFO and 64-level read data FIFO is available in the PCI target logic.
11.5.4.1 Write Cycles
For PCI master burst writes to SDRAM, the ÉlanSC520 microcontroller can sustain zero
wait states until the PCI target write FIFO is filled. As the FIFO is filling at the PCI interface,
data is being removed from the FIFO and written to SDRAM. When the SDRAM controller’s
write buffer is enabled, data can be quickly transferred from the PCI target write FIFO to
the SDRAM write buffer in zero wait states (to a non-full write buffer), allowing the PCI
target write FIFO to empty quickly. This prevents the PCI master from experiencing the
SDRAM latencies, thus freeing up the PCI bus earlier.
During PCI target write transfers to SDRAM, the Am5
x
86 CPU cache is snooped to maintain
coherency. If the CPU cache is configured in write-back cache mode and a snoop results
in a hit, the modified Am5
x
86 CPU cache line must be written back to memory prior to
allowing the PCI target write transfer to take place. When the write buffer is enabled, the
Am5
x
86 CPU cache-line write-back is posted to the write buffer, and the following PCI target
write transaction collapses on top of the previously written cache-line write-back, resulting
in a reduction in the overall number of transactions to memory.
11.5.4.2 Read Cycles
In most applications, a PCI master transfers data to SDRAM and then interrupts the
processor when the transfer is complete. The processor then usually accesses this data
in SDRAM. Since the write buffer supports read-merging, associated data that is still in the
write buffer from the PCI transfer may be immediately read by the processor, without the
overhead of first flushing the write buffer before allowing the read to occur. Also, since the
SDRAM controller allows read-around-write activity when the write buffer is enabled, the
processor reads are allowed to occur around writes that are posted in the write buffer, thus
offering a performance increase to processor read requests.
During PCI master read transfers from SDRAM, the ÉlanSC520 microcontroller’s PCI target
read FIFO is filled with data read from SDRAM. This data is then supplied to the requesting
PCI master directly from the target’s read FIFO. Since PCI bursts are linear and forward in
nature, the SDRAM controller’s read-ahead feature prefetches data (from SDRAM) forward
from the PCI master’s start address. As the ÉlanSC520 microcontroller’s PCI target read
FIFO requests data from SDRAM, it is likely that these requests will result in read buffer
hits due to prefetching, thus providing data quickly to the PCI target read FIFO.