AMD Elan SC520, Руководство пользователя

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SDRAM Controller
10-28 Élan™SC520 Microcontroller User’s Manual
10.5.9 Software Considerations
10.5.9.1 ECC Errors
The ECC logic in the SDRAM controller detects single-bit error and multi-bit errors in the
SDRAM data being accessed.
■ When a single-bit error is detected, a maskable interrupt is generated. See Chapter 15,
“Programmable Interrupt Controller”, for information on steering this interrupt.
■ When a multi-bit error is detected, a non-maskable interrupt (NMI) is generated.
The interrupt handler should read the ECC Status (ECCSTA) register (MMCR offset 21h)
logging the detection of a single-bit error (SBIT_ERR) or a multi-bit error (MBIT_ERR),
depending on which interrupt signal is generated. The physical address where the error
occurred is latched for both single-bit and multi-bit errors in the ECC Single-Bit Error
Address (ECCSBADD) register (MMCR offset 24h) and ECC Multi-Bit Error Address
(ECCMBADD) register (MMCR offset 28h), respectively. An encoded value of the data bit
position where the single-bit error occurred is also latched in the ECC_CHK_POS bit field
of the ECC Check Bit Position (ECCCKBPOS) register (MMCR offset 22h).
All latched information pertaining to an error is latched on the first occurrence and cleared
when the latch is re-enabled. Information for errors that occur
after the first occurrence, but
before the latch is re-enabled, are lost.
10.5.9.2 Buffer Disabling During SDRAM Configuration
Prior to altering the SDRAM configuration, the write buffer and read-ahead feature of the
read buffer must be disabled. This is to prevent SDRAM configuration changes while a
write buffer or read-ahead prefetch to SDRAM is in progress. During bank configuration, it
is important to not enable an SDRAM bank with the Bank Ending Address specified as 0.
10.5.9.3 Write Protection
Regions of SDRAM can be write-protected through the use of a Programmable Attribute
Region (PAR) register. A write-protected region allows read cycle access, however, data
is not written to the devices during a write cycle access. When writing to a region that is
write-protected, an SDRAM write cycle still occurs; however, the SDQM3–SDQM0 data
mask signals are active throughout the cycle to prevent the data from being written to the
devices. If ECC is enabled and a noncomplete doubleword access is write-protected, the
SDRAM controller does not generate a read-modify-write cycle.
10.5.10 Latency
The SDRAM controller’s write buffer and read buffer are designed to enhance the memory
system’s bandwidth and performance. When enabled, the write buffer decouples master
write or burst write activity from incurring the SDRAM access latency penalty along with
the overhead associated with SDRAM refresh cycles. When enabled, the read-ahead
feature of the read buffer decouples master read activity from incurring the SDRAM latency
penalty on read buffer hits. For more information, see Chapter 11, “Write Buffer and Read
Buffer”.
SDRAM devices require periodic refresh cycles to maintain data integrity within the device.
This SDRAM activity must occur at fixed intervals as high priority requests. In the event
that a data access request and a refresh cycle request occur at the same time, the data
access request is stalled until the higher priority refresh cycle is complete. Devices that can
tolerate a slower refresh period result in a system with less refresh overhead, leaving
SDRAM free for data access requests. To support these devices, the ÉlanSC520
microcontroller provides an adjustable refresh rate of 7.8
µ
s, 15.6
µ
s, 31.2
µ
s or 62.5
µ
s.