PCI Bus Host Bridge
Élan™SC520 Microcontroller User’s Manual
9-7
It is up to the system designer to choose the accuracy of the crystal used with the ÉlanSC520
microcontroller. The 33.000-MHz frequency provides a better guard band than the 33.333-
MHz crystal. In practice, most PCI devices tolerate both frequencies, but it is important to
be aware of the impact of choosing the crystal on this potential violation of the PCI bus
specifications. The PCI bus specification requires that the minimum clock period be 30 ns.
9.4
REGISTERS
The PCI host bridge configuration registers specific to the ÉlanSC520 microcontroller are
memory-mapped in ÉlanSC520 microcontroller configuration space. These registers are
listed in Table 9-1. Table 9-2 lists the direct-mapped registers used to configure the PCI
bus host bridge. The standard PCI configuration space header registers supported on the
ÉlanSC520 microcontroller are shown in Table 9-3 as PCI indexed registers.
Table 9-1
PCI Host Bridge Registers—Memory-Mapped
Register
Mnemonic
MMCR
Offset
Address
Function
Host Bridge Control
HBCTL
60h
PCI reset, target FIFO purge enable, automatic
delayed transaction enable, and master write
posting enable
Host Bridge Target Interrupt
Control
HBTGTIRQCTL
62h
Target interrupt or NMI select and interrupt
enables: delayed transaction time-out, address
parity, and data parity
Host Bridge Target Interrupt
Status
HBTGTIRQSTA
64h
Target interrupt status: delayed transaction time-
out, address parity, data parity; target interrupt
identification
Host Bridge Master Interrupt
Control
HBMSTIRQCTL
66h
Master interrupt or NMI select and interrupt
enables: retry time-out, target abort, master
abort, system error, received parity error,
detected parity error
Host Bridge Master Interrupt
Status
HBMSTIRQSTA
68h
Master interrupt status: retry time-out, target
abort, master abort, system error, received
parity error, detected parity error; master
command interrupt identification
Host Bridge Master Interrupt
Address
MSTINTADD
6Ch
Master address interrupt identification
Interrupt Pin Polarity
INTPINPOL
D10h
Polarity of external interrupt sources (INTA–
INTD and GPIRQ10–GPIRQ0)
PCI Host Bridge Interrupt
Mapping
PCIHOSTMAP
D14h
System arbiter and PCI Host Bridge interrupt
mapping to any of 22 available interrupt
channels or NMI, PCI NMI enable control
PCI Interrupt A Mapping
PCIINTAMAP
D30h
PCI INTA mapping
PCI Interrupt B Mapping
PCIINTBMAP
D31h
PCI INTB mapping
PCI Interrupt C Mapping
PCIINTCMAP
D32h
PCI INTC mapping
PCI Interrupt D Mapping
PCIINTDMAP
D33h
PCI INTD mapping
Содержание Elan SC520
Страница 1: ...lan SC520 Microcontroller User s Manual Order 22004A...
Страница 4: ...iv lan SC520 Microcontroller User s Manual...
Страница 28: ...Introduction xxviii lan SC520 Microcontroller User s Manual...
Страница 42: ...Architectural Overview 1 14 lan SC520 Microcontroller User s Manual...
Страница 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...
Страница 108: ...Clock Generation and Control 5 10 lan SC520 Microcontroller User s Manual...
Страница 118: ...Reset Generation 6 10 lan SC520 Microcontroller User s Manual...
Страница 148: ...System Arbitration 8 24 lan SC520 Microcontroller User s Manual...
Страница 214: ...SDRAM Controller 10 36 lan SC520 Microcontroller User s Manual...
Страница 230: ...Write Buffer and Read Buffer 11 16 lan SC520 Microcontroller User s Manual...
Страница 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...
Страница 316: ...Programmable Interval Timer 16 8 lan SC520 Microcontroller User s Manual...
Страница 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...
Страница 346: ...Real Time Clock 20 12 lan SC520 Microcontroller User s Manual...
Страница 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...
Страница 414: ...AMDebug Technology 26 8 lan SC520 Microcontroller User s Manual...