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48

Signal and Power-Up Requirements

Chapter 9

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Preliminary Information

Clock Multiplier
Selection (FID[3:0])

The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct serial initialization packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Athlon system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.

For more information about FID[3:0], see “FID[3:0] Pins” on
page 75.

Serial Initialization Packet (SIP) Protocol.

R e f e r t o

A M D A t h l o n ™

System Bus Specification

, order# 21902 for details of the SIP

protocol.

9.2

Processor Warm Reset Requirements

Northbridge Reset
Pins

RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.

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Содержание ATHLON 8

Страница 1: ...Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Publication 25175 Rev H Issue Date March 2003 TM...

Страница 2: ...s to specifications and prod uct descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publ...

Страница 3: ...m 16 4 3 Clock Control 18 5 CPUID Support 19 6 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 21 6 1 Part Specific Electrical and Thermal Specifications for Advanced 266 FS...

Страница 4: ...8 14 APIC Pins AC and DC Characteristics 44 9 Signal and Power Up Requirements 45 9 1 Power Up Requirements 45 Signal Sequence and Timing Description 45 Clock Multiplier Selection FID 3 0 48 9 2 Proc...

Страница 5: ...I Pin 78 PGA Orientation Pins 78 PLL Bypass and Test Pins 78 PWROK Pin 78 SADDIN 1 0 and SADDOUT 1 0 Pins 79 Scan Pins 79 SMI Pin 79 STPCLK Pin 79 SYSCLK and SYSCLK 79 THERMDA and THERMDC Pins 79 VCCA...

Страница 6: ...6 Table of Contents AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 7: ...6 Figure 7 Processor Connect State Diagram 17 Figure 8 SYSCLK Waveform 24 Figure 9 SYSCLK Waveform 28 Figure 10 VCC_CORE Voltage Waveform 35 Figure 11 SYSCLK and SYSCLK Differential Clock Signals 37 F...

Страница 8: ...8 List of Figures AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 9: ...C and DC Characteristics 34 Table 13 Absolute Ratings 36 Table 14 SYSCLK and SYSCLK DC Characteristics 37 Table 15 AMD Athlon System Bus DC Characteristics 38 Table 16 General AC and DC Characteristic...

Страница 10: ...March 2003 Preliminary Information Table 28 VID 4 0 Code to Voltage Definition 80 Table 29 Constants and Variables for the Ideal Diode Equation 83 Table 30 Constants and Variables Used in Temperature...

Страница 11: ...OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 on page 53 renamed Figure 14 AMD Athlon XP Processor Model 8 Part Number 27291 OPGA Package on page 52 and added Figure...

Страница 12: ...imensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 on page 51 In Chapter 12 revised Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 on page 81 August 2002 C Public revisi...

Страница 13: ...et capability digital content creation digital photo editing digital video image compression video encoding for streaming over the Internet soft DVD commercial 3D modeling workstation class computer a...

Страница 14: ...ented in the AMD Athlon XP processor model 8 includes new integer multimedia instructions and software directed data movement instructions for optimizing such applications as digital content creation...

Страница 15: ...processor model 8 is compatible with motherboards based on Socket A Figure 1 shows a typical AMD Athlon XP processor model 8 system block diagram Figure 1 Typical AMD Athlon XP Processor Model 8 Syst...

Страница 16: ...4 Overview Chapter 1 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 17: ...impedance controlled push pull low voltage swing signaling technology contained within the Socket A socket For more information see AMD Athlon System Bus Signals on page 6 Chapter 11 Pin Descriptions...

Страница 18: ...impedance of the motherboard by two external resistors connected to the ZN and ZP pins See ZN and ZP Pins on page 80 for more information 2 4 AMD Athlon System Bus Signals The AMD Athlon system bus i...

Страница 19: ...gram SDATA 63 0 SDATAINCLK 3 0 SDATAOUTCLK 3 0 Data SADDIN 14 2 SADDINCLK Probe SysCMD SADDOUT 14 2 SADDOUTCLK VID 4 0 FID 3 0 A20M CLKFWDRST CONNECT COREFB COREFB FERR IGNNE INIT INTR NMI PROCRDY PWR...

Страница 20: ...8 Logic Symbol Diagram Chapter 3 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 21: ...agement states of the processor The figure includes the ACPI Cx naming convention for these states Figure 3 AMD Athlon XP Processor Model 8 Power Management States C1 Halt C0 Working4 Execute HLT SMI...

Страница 22: ...is disconnected then issue a Stop Grant special cycle When STPCLK is deasserted the processor will exit the Stop Grant state and re enter the Halt state The processor will issue a Halt special cycle...

Страница 23: ...nt state the processor exits the Stop Grant state and the reset process begins There are two mechanisms for asserting STPCLK hardware and software The Southbridge can force STPCLK assertion for thrott...

Страница 24: ...nt state When probe activity is completed the processor only returns to a low power state after the Northbridge disconnects the AMD Athlon system bus again 4 2 Connect and Disconnect Protocol Signific...

Страница 25: ...ssing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransport technology This note applies to current chipset implementation alternate chipset i...

Страница 26: ...rant state 2 When the processor recognizes STPCLK asserted it enters the Stop Grant state and then issues a Stop Grant special cycle 3 When the special cycle is received by the Northbridge it deassert...

Страница 27: ...moves the processor from the Stop Grant state and connects it to the system bus 1 The Southbridge deasserts STPCLK informing the processor of a wake event 2 When the processor recognizes STPCLK deasse...

Страница 28: ...special cycle from the processor 4 No probes are pending 5 PROCRDY is deasserted 6 A probe needs service 7 PROCRDY is asserted 8 Three SYSCLK periods after CLKFWDRST is deasserted Although reconnecte...

Страница 29: ...RST is deasserted by the Northbridge 6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted Action A CLKFWDRST is asserted by the Northbridge B Issue a Connect special cycle C Retur...

Страница 30: ...Clock Control The processor implements a Clock Control CLK_Ctl MSR address C001_001Bh that determines the internal clock divisor when the AMD Athlon system bus is disconnected Refer to the AMD Athlon...

Страница 31: ...rmation about the processor vendor type name etc and its capabilities Software can make use of this information to accurately tune the system for maximum performance and benefit to users For informati...

Страница 32: ...20 CPUID Support Chapter 5 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 33: ...ations This chapter describes the electrical specifications that are unique to the advanced 266 front side bus FSB AMD Athlon XP processor model 8 6 1 Part Specific Electrical and Thermal Specificatio...

Страница 34: ...ee Figure 3 AMD Athlon XP Processor Model 8 Power Management States on page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of...

Страница 35: ...4 A 37 6 A 8 9 A 5 4 A 68 3 W 62 0 W 2133 2600 1 65 V 41 4 A 37 6 A 8 9 A 5 4 A 68 3 W 62 0 W Notes 1 See Figure 3 AMD Athlon XP Processor Model 8 Power Management States on page 9 2 The maximum Stop...

Страница 36: ...s t3 Low Time 1 05 ns t4 Fall Time 2 ns t5 Rise Time 2 ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon system bus...

Страница 37: ...apacitance on input Clocks 4 25 pF COUT Capacitance on output Clocks 4 12 pF Sync TVAL RSTCLK to Output Valid 250 2000 ps 4 5 TSU Setup to RSTCLK 500 ps 4 6 THD Hold from RSTCLK 1000 ps 4 6 Notes 1 Ri...

Страница 38: ...26 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications Chapter 6 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 39: ...MD Athlon XP Processor Model 8 Power Management States on page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process a...

Страница 40: ...t3 Low Time 1 0 ns t4 Fall Time 2 ns t5 Rise Time 2 ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon system bus c...

Страница 41: ...ta Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input Clocks 4 25 pF COUT Capacitance on output Clocks 4 12 pF Sync TVAL RSTCLK to Output Valid 800 2000 ps 4 5 TSU Setup to...

Страница 42: ...30 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications Chapter 7 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 43: ...ained in each group Table 8 Interface Signal Groupings Signal Group Signals Notes AMD Athlon System Bus SADDIN 14 2 SADDOUT 14 2 SADDINCLK SADDOUTCLK SFILLVAL SDATAINVAL SDATAOUTVAL SDATA 63 0 SDATAIN...

Страница 44: ...d RSTCLK RSTCLK PLLBYPASSCLK PLLBYPASSCLK See Advanced 266 FSB AMD Athlon XP Processor Model 8 SYSCLK and SYSCLK AC Characteristics on page 24 Advanced 333 FSB AMD Athlon XP Processor Model 8 SYSCLK a...

Страница 45: ...haracteristics Parameter Description Min Max IOL Output Current Low 6 mA VOH Output High Voltage 5 25 V Note The VID pins are either open circuit or pulled to ground It is recommended that these pins...

Страница 46: ...for VCC_CORE See Figure 10 on page 35 for a graphical representation of the VCC_CORE waveform Table 12 VCC_CORE AC and DC Characteristics Symbol Parameter Limit in Working State Units VCC_CORE_DC_MAX...

Страница 47: ...waveform response to perturbation The tmin_AC negative AC transient excursion time and tmax_AC positive AC transient excursion time represent the maximum allowable time below or above the DC tolerance...

Страница 48: ...y affect long term reliability or result in functional damage Table 13 lists the maximum absolute ratings of operation for the AMD Athlon XP processor model 8 Table 13 Absolute Ratings Parameter Descr...

Страница 49: ...K and SYSCLK signals Figure 11 SYSCLK and SYSCLK Differential Clock Signals Table 14 SYSCLK and SYSCLK DC Characteristics Symbol Description Min Max Units VThreshold DC Crossing before transition is d...

Страница 50: ...VREF Tristate Leakage Pulldown VIN VREF Nominal 100 A VIH Input High Voltage VREF 200 VCC_CORE 500 mV VIL Input Low Voltage 500 VREF 200 mV ILEAK_P Tristate Leakage Pullup VIN VSS Ground 1 mA ILEAK_N...

Страница 51: ...ltage range 2 Values specified at nominal VCC_CORE Scale parameters between VCC_CORE minimum and VCC_CORE maximum 3 IOL and IOH are measured at VOL maximum and VOH minimum respectively 4 Synchronous i...

Страница 52: ...are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized 7 In asynchronous operation the signal mu...

Страница 53: ...utomated test equipment ATE to test for validity on open drain pins Refer to Table 16 General AC and DC Characteristics on page 39 for timing requirements Figure 12 General ATE Open Drain Test Circuit...

Страница 54: ...or information about calculations for the ideal diode equation and temperature offset correction see Appendix A Thermal Diode Calculations on page 77 Table 17 Thermal Diode Electrical Characteristics...

Страница 55: ...e to the processor Systems that do not implement thermal protection circuitry or that do not react within the time specified by TSD_DELAY can cause thermal damage to the processor during the unlikely...

Страница 56: ...ature of the processor The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event Refer to AMD Athlon...

Страница 57: ...and Timing Description Figure 13 shows the relationship between key signals in the system during a power up sequence This figure details the requirements of the processor Figure 13 Signal Relationship...

Страница 58: ...conds from the 3 3 V supply being within specification This delay ensures that the system clock SYSCLK SYSCLK is operating within specification when PWROK is asserted The processor core voltage VCC_CO...

Страница 59: ...eet the timing requirements as defined in Table 16 General AC and DC Characteristics on page 39 The processor should not switch between the ring oscillator and the PLL after the initial assertion of P...

Страница 60: ...FID 3 0 code The SIP is sent to the processor using the SIP protocol This protocol uses the PROCRDY CONNECT and CLKFWDRST signals that are synchronous to SYSCLK For more information about FID 3 0 see...

Страница 61: ...sfer from the die to an approved heat sink Any heat sink design should avoid loads on corners and edges of die The OPGA package has compliant pads that serve to bring surfaces in planar contact Tool a...

Страница 62: ...sors Model 8 with a CPUID of 680 Letter or Symbol Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 E9 1 66 1 96 D1 E1 45 72 BSC G H 4 50 D2...

Страница 63: ...sors Model 8 with a CPUID of 681 Letter or Symbol Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 E9 1 66 1 96 D1 E1 45 72 BSC G H 4 50 D2...

Страница 64: ...52 Mechanical Data Chapter 10 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information Figure 14 AMD Athlon XP Processor Model 8 Part Number 27291 OPGA Package...

Страница 65: ...on XP Processors Model 8 with a CPUID of 681 Letter or Symbol Minimum Dimension1 Maximum Dimension1 Letter or Symbol Minimum Dimension1 Maximum Dimension1 D E 49 27 49 78 G H 4 50 D1 E1 45 72 BSC A 1...

Страница 66: ...54 Mechanical Data Chapter 10 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information Figure 15 AMD Athlon XP Processor Model 8 Part Number 27648 OPGA Package...

Страница 67: ...ations and a cross referenced listing of pin locations to signal names 11 1 Pin Diagram and Pin Name Abbreviations Figure 16 on page 56 shows the staggered pin grid array PGA for the AMD Athlon XP pro...

Страница 68: ...CC VSS VSS VSS VSS R S SCNCK1 SCNINV SCNCK2 THDA NC SD 7 SD 15 SD 6 S T VSS VSS VSS VSS VCC VCC VCC VCC T U TDI TRST TDO THDC NC SD 5 SD 4 NC U V VCC VCC VCC VCC VSS VSS VSS VSS V W FID 0 FID 1 VREF_S...

Страница 69: ...KEY NC CLKIN CLKIN 17 18 VSS VSS VSS VSS VCC VCC VCC VCC 18 19 NC SD 59 SD 58 NC NC NC RCLK RCLK 19 20 VCC VCC VCC VCC VSS VSS VSS VSS 20 21 SD 57 SD 56 SD 36 NC NC CLKFR K7CO K7CO 21 22 VSS VSS VSS V...

Страница 70: ...AG1 FID 0 W1 FID 1 W3 FID 2 Y1 FID 3 Y3 FLUSH AL3 FSB0 FSB_Sense 0 AG31 FSB1 FSB_Sense 1 AH30 IGNNE AJ1 INIT AJ3 INTR AL1 K7CO K7CLKOUT AL21 K7CO K7CLKOUT AN21 KEY G7 KEY G9 KEY G15 KEY G17 KEY G23 K...

Страница 71: ...me Abbreviations continued Abbreviation Full Name Pin NC AJ19 NC AJ27 NC AK8 NC AL7 NC AL9 NC AL11 NC AL25 NC AL27 NC AM8 NC AN7 NC AN9 NC AN11 NC AN25 NC AN27 NMI AN3 PICCLK N1 PICD 0 PICD 0 N3 PICD...

Страница 72: ...2 SCANCLK2 S5 SCNINV SCANINTEVAL S3 SCNSN SCANSHIFTEN Q5 SD 0 SDATA 0 AA35 SD 1 SDATA 1 W37 SD 2 SDATA 2 W35 Table 24 Pin Name Abbreviations continued Abbreviation Full Name Pin SD 3 SDATA 3 Y35 SD 4...

Страница 73: ...INCLK 0 W33 SDIC 1 SDATAINCLK 1 J35 SDIC 2 SDATAINCLK 2 E27 SDIC 3 SDATAINCLK 3 E15 SDINV SDATAINVALID AN33 SDOC 0 SDATAOUTCLK 0 AE35 SDOC 1 SDATAOUTCLK 1 C37 Table 24 Pin Name Abbreviations continued...

Страница 74: ..._CORE T36 VCC VCC_CORE V2 VCC VCC_CORE V4 VCC VCC_CORE V6 VCC VCC_CORE V8 Table 24 Pin Name Abbreviations continued Abbreviation Full Name Pin VCC VCC_CORE X30 VCC VCC_CORE X32 VCC VCC_CORE X34 VCC VC...

Страница 75: ...AJ23 VID 0 L1 VID 1 L3 VID 2 L5 VID 3 L7 VID 4 J7 VREF_S VREF_SYS W5 VSS B2 VSS B6 VSS B10 VSS B14 VSS B18 VSS B22 VSS B26 VSS B30 VSS B34 VSS D6 VSS D10 VSS D14 VSS D18 Table 24 Pin Name Abbreviation...

Страница 76: ...VSS AB4 VSS AB6 VSS AD32 VSS AD34 VSS AD36 VSS AF2 VSS AF4 VSS AF12 VSS AF16 VSS AH12 VSS AH16 VSS AH20 VSS AH24 VSS AH28 VSS AH32 VSS AH34 Table 24 Pin Name Abbreviations continued Abbreviation Full...

Страница 77: ...push pull mode driven by a single source O indicates open drain mode that allows devices to share the pin Note The AMD Athlon processor supports push pull drivers For more information see Push Pull PP...

Страница 78: ...O P A35 SDATA 40 P B G A37 SDATA 30 P B P B2 VSS B4 VCC_CORE B6 VSS B8 VCC_CORE B10 VSS B12 VCC_CORE B14 VSS B16 VCC_CORE B18 VSS B20 VCC_CORE B22 VSS B24 VCC_CORE B26 VSS B28 VCC_CORE B30 VSS B32 VCC...

Страница 79: ...SDATA 46 P B P E25 NC Pin page 78 E27 SDATAINCLK 2 P I G E29 SDATA 33 P B P E31 SDATA 32 P B P Table 25 Cross Reference by Pin Location Pin Name Description L P R E33 NC Pin page 78 E35 SDATA 31 P B P...

Страница 80: ...in page 78 H32 NC Pin page 78 H34 VSS H36 VSS J1 SADDOUT 0 page 79 P O J3 SADDOUT 1 page 79 P O Table 25 Cross Reference by Pin Location Pin Name Description L P R J5 NC Pin page 78 J7 VID 4 page 79 O...

Страница 81: ...G Q37 SDATA 16 P B G R2 VCC_CORE R4 VCC_CORE R6 VCC_CORE R8 VCC_CORE R30 VSS R32 VSS Table 25 Cross Reference by Pin Location Pin Name Description L P R R34 VSS R36 VSS S1 SCANCLK1 page 79 P I S3 SCA...

Страница 82: ...page 78 Y33 NC Pin page 78 Y35 SDATA 3 P B G Y37 SDATA 12 P B P Z2 VCC_CORE Z4 VCC_CORE Table 25 Cross Reference by Pin Location Pin Name Description L P R Z6 VCC_CORE Z8 VCC_CORE Z30 VSS Z32 VSS Z34...

Страница 83: ...AF28 NC Pin page 78 Table 25 Cross Reference by Pin Location Pin Name Description L P R AF30 NC Pin page 78 AF32 NC Pin page 78 AF34 VCC_CORE AF36 VCC_CORE AG1 FERR page 75 P O AG3 RESET I AG5 NC Pin...

Страница 84: ...DIN 0 page 79 P I AJ31 SFILLVALID P I G AJ33 SADDINCLK P I G AJ35 SADDIN 6 P I P AJ37 SADDIN 3 P I G Table 25 Cross Reference by Pin Location Pin Name Description L P R AK2 VSS AK4 VSS AK6 CPU_PRESENC...

Страница 85: ...S AM26 VCC_CORE AM28 VSS AM30 VCC_CORE AM32 VSS AM34 VCC_CORE AM36 VSS AN1 No Pin page 78 AN3 NMI P I AN5 SMI P I AN7 NC Pin page 78 AN9 NC Pin page 78 Table 25 Cross Reference by Pin Location Pin Nam...

Страница 86: ...21902 for information about the system bus pins PROCRDY PWROK RESET SADDIN 14 2 SADDINCLK SADDOUT 14 2 SADDOUTCLK SDATA 63 0 SDATAINCLK 3 0 SDATAINVALID SDATAOUTCLK 3 0 SDATAOUTVALID SFILLVALID Analog...

Страница 87: ...nce of a processor in the Socket A style socket DBRDY and DBREQ Pins DBRDY and DBREQ are routed to the debug connector DBREQ is tied to VCC_CORE with a pullup resistor FERR Pin FERR is an output to th...

Страница 88: ...h to above 2 5 V they must be electrically isolated from the processor For information about the FID 3 0 isolation circuit see the AMD Athlon Processor Based Motherboard Design Guide order 24363 Table...

Страница 89: ...s the truth table to determine the FSB of desktop processors The FSB_Sense 1 0 pins are 3 3 V tolerant FLUSH Pin FLUSH must be tied to VCC_CORE with a pullup resistor If a debug connector is implement...

Страница 90: ...re information NC Pins The motherboard should provide a plated hole for an NC pin The pin hole should not be electrically connected to anything NMI Pin NMI is an input from the system that causes a no...

Страница 91: ...r power mode and issue a Stop Grant special cycle SYSCLK and SYSCLK SYSCLK and SYSCLK are differential input clock signals provided to the PLL of the processor from a system clock generator See CLKIN...

Страница 92: ...P AE5 are the push pull compensation circuit pins In Push Pull mode selected by the SIP parameter SysPushPull asserted ZN is tied to VCC_CORE with a resistor that has a resistance matching the impedan...

Страница 93: ...ed Front Side Bus FSB C 266 D 333 Size of L2 Cache 3 256 Kbytes Die Temperature T 90 C V 85 C Operating Voltage L 1 50 V U 1 60 V K 1 65 V Package Type D OPGA Model Number 1600 operates at 1400 MHz2 1...

Страница 94: ...82 Ordering Information Chapter 12 AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 95: ...8 For electrical information about this thermal diode see Table 17 Thermal Diode Electrical Characteristics on page 42 Ideal Diode Equation The ideal diode equation uses the variables and constants d...

Страница 96: ...Correction A temperature offset may be required to correct the value measured by a temperature sensor An offset is necessary if a difference exists between the lumped ideality factor of the processor...

Страница 97: ...r further details Equation 3 shows the equation for calculating the lumped ideality factor nf lumped in sensors that do not employ series resistance cancellation Equation 4 shows the equation for calc...

Страница 98: ...86 Appendix A Thermal Diode Calculations AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

Страница 99: ...e letter Signal Ranges In a range of signals the highest and lowest signal numbers are contained in brackets and separated by a colon for example D 63 0 Reserved Bits and Signals Signals or bus bits m...

Страница 100: ...nvention The byte with the address xx xx00 is in the least significant byte position little end In byte diagrams bit positions are numbered from right to left the little end is on the right and the bi...

Страница 101: ...in this document Table 31 Abbreviations Abbreviation Meaning A Ampere F Farad G Giga Gbit Gigabit Gbyte Gigabyte GHz Gigahertz H Henry h Hexadecimal K Kilo Kbyte Kilobyte lbf Foot pound M Mega Mbit Me...

Страница 102: ...Interconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input Output System BIST Built In Self Test BIU Bus Interface Unit CPGA Ceramic Pin Grid A...

Страница 103: ...NMI Non Maskable Interrupt OD Open Drain OPGA Organic Pin Grid Array PA Physical Address PBGA Plastic Ball Grid Array PCI Peripheral Component Interconnect PDE Page Directory Entry PDT Page Directory...

Страница 104: ...Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TTL Transistor Transistor Logic VAS Virtual Address Space VPA Virt...

Страница 105: ...Web site http www amd com AMD Athlon Processor x86 Code Optimization Guide order 22007 AMD Processor Recognition Application Note order 20734 Methodologies for Measuring Temperature on AMD Athlon and...

Страница 106: ...94 Appendix B Conventions and Abbreviations AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Preliminary Information...

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