AMD Am186 CC, Руководство пользователя

Страница: 221 / 376

Asynchronous Serial Ports (UARTs)
Am186™CC/CH/CU Microcontrollers User’s Manual 13-13
data register. The new status is ORed with the previous status, possibly accumulating status
over multiple frames. For this reason, the status register must be read before the receive
data register to ensure that the status being read is for the current frame. Set status bits
must be cleared by software. When extended reads are enabled, the high byte of the
HSPRXD register contains the status associated with the current frame; however, status
continues to accumulate in the HSPSTAT register. The RDR bit is set when data is available
in the receive FIFO (the value of this bit can be read from the HSPSTAT register or from
the high-byte of an extended read). When the RDR bit is set, valid data is present in the FIFO.
If receive status interrupts are enabled, an interrupt can be generated at the time an error
is detected. The interrupt service routine must read data out of the FIFO until the data which
generated the interrupt reaches the top of the FIFO. At this point, the status register reports
the error condition.
Data to be transmitted is written to the Transmit Data register as in non-FIFO mode.
However, the transmit status reflects the disposition of the FIFO. When the FIFO is not full,
the Transmit Holding Register Empty (THRE) bit is set, indicating that the transmitter can
accept more data. When the FIFO is completely full, the THRE bit is 0. When the transmit
FIFO and the transmit shift register are completely empty, the Transmitter Empty (TEMT)
bit is set. At this point, the transmitter or FIFO can be disabled without loss of data.
13.5.4 CTS/RTR Hardware Flow Control
The microcontroller supports CTS/RTR hardware flow control. Each UART port is provided
with two data signals (TXD_U and RXD_U for the UART, and TXD_HU and RXD_HU for
the High-Speed UART) and two flow control signals (CTS_U and RTR_U for the UART, and
CTS_HU and RTR_HU for the High-Speed UART). Hardware flow control is enabled when
the FC bit in the (H)SPCON0 register is set to 1.
In the CTS/RTR protocol, the receiver asserts clear-to-send (CTS) whenever there is room
in the receiver for more data. The transmitting device should sample CTS before beginning
transmission of each frame. CTS is deasserted when the start bit is detected for the last
frame that can be read without data loss. When FIFOs are disabled, CTS is deasserted
after the start bit for each frame is detected and remains deasserted until the data is read
from the receive data register. When the receive FIFO is enabled, CTS is deasserted after
the start bit is received for the last frame that will fit in the FIFO.
The transmitter samples ready-to-receive (RTR) before transmitting the start bit of each
frame. The RTR signal is not sampled during frame transmission. This allows the receiving
device to deassert RTR any time before the end of the stop bit. The transmitter does not
begin transmitting the start bit for the next frame while RTR is deasserted.
The use of hardware flow control can eliminate the possibility of overrun errors—data loss
due to reception of new data before the last received data has been read. However, there
can be an adverse effect on data throughput. For example, in the case where there is no
receive FIFO, transmission of a second data frame cannot begin until the previous frame's
data has been read. Without hardware flow control, transmission of the next frame may
begin immediately, providing the receiver with one frame time to read the previous frame's
data without data loss. Use of FIFOs or DMA reduces the impact of hardware flow control
on data throughput.
In multidrop systems, typically using the address bit feature of the microcontroller's serial
ports, hardware flow control should not be enabled, or must be restricted to a single pair
of active UARTs.