Chip Selects
5-8
Am186™CC/CH/CU Microcontrollers User’s Manual
PCS7–PCS0 can overlap any UCS or LCS space which has been configured for DRAM.
(Overlap of the PCS signals with UCS or LCS in non-DRAM mode is not recommended.)
Overlapping PCS with DRAM is fully supported as long as the PCS chip selects are
programmed for a greater or equal number of wait states than that of the DRAM.
Note: Because of how the DRAM access is terminated, it is illegal to allocate a PCS space
with fewer wait states than the DRAM it is overlapping.
If PCS overlaps LCS or UCS configured for DRAM, PCS access takes precedence over
the LCS or UCS access. The DRAM controller asserts RAS and stops the CAS signal from
asserting. This does not modify the contents of the DRAM, and the access continues as a
normal PCS access.
Overlapping the PCS chip selects with DRAM makes a 2-Kbyte block of the DRAM
inaccessible. In its place, the peripherals associated with the PCS can be accessed. This
is especially useful when the entire memory space is used with two banks of DRAM or a
bank of DRAM and a 512-Kbyte Flash memory.
5.5.4
Overlapping Chip Selects
Although programming the various chip selects on the Am186CC/CH/CU microcontrollers
so that multiple chip select signals are asserted for the same physical address is not
recommended, it may be unavoidable in some systems. Note that configuring PCS in I/O
space with LCS or any other chip select configured for memory address 0 is not considered
overlapping of the chip selects. Overlapping chip selects refers to configurations where
more than one chip select asserts for the same physical address. PCS overlaps are allowed
when UCS or LCS are configured for DRAM. For more information about this overlapping,
see “Selecting DRAM Using the Chip Selects” on page 5-7.
In systems where the chip selects must overlap, the chip selects whose assertions overlap
must have the same configuration for ready (external ready required or not required) and
for the number of wait states to be inserted into the cycle by the processor.
The peripheral control block (PCB) is accessed using
internal signals. These internal signals
function as chip selects configured with zero wait states and no external ready. Therefore,
the PCB can reside at addresses that overlap
external chip select signals if those external
chip selects are programmed to zero wait states with no external ready required.
When overlapping an additional chip select with either the LCS or UCS chip selects, note
that setting the Disable Address (DA) bit in the LMCS or UMCS register disables the address
from being driven on the AD bus for all accesses for which the associated chip select is
asserted, including any accesses for which multiple chip selects assert.
The MCS and PCS chip select pins can be configured as either chip selects or as PIO
inputs or outputs. However, the ready and wait state generation logic for these chip selects
is in effect regardless of their configurations as chip selects or PIOs. This means that if
these chip selects are enabled (by a write to the MMCS and MPCS registers for the MCS
chip selects, or by a write to the PACS and MPCS registers for the PCS chip selects), the
ready and wait state programming for these signals must agree with the programming for
any other chip selects with which their assertion would overlap if they were configured as
chip selects.
Failure to configure overlapping chip selects with the same ready and wait state
requirements may cause the processor to hang with the appearance of waiting for a ready
signal. This behavior can occur even in a system in which ready is always asserted (ARDY
or SRDY tied High).
Содержание Am186 CC
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Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...