Chapter 2: Quick Start Tutorial
2–3
Procedures
© December 2009 Altera Corporation
TimeQuest Timing Analyzer Quick Start Tutorial
Step 5: Create a Post-Map Timing Netlist
Before specifying the timing requirements, create a timing netlist. You can create a
timing netlist from a post-map or post-fit database. In this step, create a timing netlist
from the post-map database you created in
“Step 3: Perform Initial Compilation”
with
the procedures in
Table 2–5
.
1
You cannot use the
Create Timing Netlist
command in the
Tasks
pane to create a
post-map timing netlist. By default, the
Create Timing Netlist
requires a post-fit
database.
Step 6: Specify Timing Requirements
You must define two clocks in the
fir_filter
design. Refer to
Table 2–6
for a list of
properties for each clock.
Create the clocks in the
fir_filter
design and assign the proper clock ports with the
procedures in
Table 2–7
.
f
For more information about constraints supported by the TimeQuest Timing
Analyzer, refer to the
TimeQuest Timing Analyzer
chapter in volume 3 of the
Quartus II
Handbook
.
1
By default, the
create_clock
command assumes a 50/50 duty cycle if the
-waveform
option is not used.
Table 2–5.
Creating a Post-Map Timing Netlist
TimeQuest Timing Analyzer GUI
TimeQuest Timing Analyzer Console
1. On the Netlist menu, click
Create Timing Netlist
. The
Create Timing Netlist
dialog box appears.
2. Under
Input netlist
, select
Post-Map
.
3. Click
OK
.
Type:
create_timing_netlist –post_map
r
Table 2–6.
Clocks in fir_filter Design
Clock Port Name
Requirement
clk
50 MHz with a 50/50 duty cycle
clkx2
100 MHz with a 60/40 duty cycle
Table 2–7.
Creating Clocks and Assigning Clock Ports
TimeQuest Timing Analyzer
GUI
TimeQuest Timing Analyzer Console
1. On the Constraints menu,
click
Create Clock
. The
Create Clock
dialog box
appears.
2. Specify the parameters in
Table 2–2
for the 50 MHz
clock. Repeat these step for
the 100 MHz clock.
Type:
#create the 50 MHz (20 ns) clock
create_clock –period 20 [get_ports clk]
r
#create the 100 MHz (10 ns) clock
create_clock –period 10 –waveform {0 6} [get_ports clkx2]
r
