Altera MAX 10 series, Руководство пользователя

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Figure 3-2: FSM of the Power Management Controller
Awake
Sleep
Entering Exiting
Sleep = 1 clk_ena = 1 &
ioe = 1
clk_ena = 0 &
ioe = 0 Sleep = 0
Entering State
When the power management controller detects a sleep event, the FSM transitions to the Entering state
and performs power-down operation on I/O buffers and GCLK networks. A sleep event is detected when
the
sleep
signal is asserted. A sleep event could be triggered by an internal or external request.
Sleep State
After the power-down operation on I/O buffers and GCLK networks, the FSM transitions to the Sleep
state and waits for the wake-up event. This state is the sleep mode state.
Exiting State
When the power management controller detects a wake-up event, the FSM transitions to the Exiting state
and performs power-up operation on I/O buffers and GCLK networks. A wake-up event is detected when
the
sleep
signal is de-asserted. A wake-up event could be triggered by an internal or external request such
as interruption or time-out on some counters..
Awake State
After the power-up operation on I/O buffers and GCLK networks, the FSM transitions to the Awake state.
This process repeats when a sleep event is initiated again.
Entering or Exiting Sleep Mode
During power-up and configuration modes, the
sleep
signal must be low. When the
sleep
signal is
asserted, the device immediately enters sleep mode. Upon entering sleep mode, the functionality of the
device such as GCLK networks and I/O buffers are dynamically powered down—to minimize dynamic
power dissipation. All configuration data is retained when the device is in the sleep mode.
UG-M10PWR
2015.11.02
Entering State
3-3
Power Management Controller Reference Design
Altera Corporation
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