Enpirion
®
Power Evaluation Board User Guide
EN5367QI PowerSoC
Figure 3: SMA Connector for External Clock Input
Power down the device. Move ENA into disable position. Connect the clock signal as
just indicated. The clock signal should be clean and have a frequency in the range of
the nominal frequency
±
15%; amplitude 0 to 2.5 volts with a duty cycle between 20 and
80%. With SYNC signal disabled, power up the device and move ENA jumper to
Enabled position. The device is now powered up and outputting the desired voltage.
The device is switching at its free running frequency. The switching waveform may be
observed between test points SW and GND. Now enabling the SYNC signal will
automatically phase lock the internal switching frequency to the externally applied
frequency as long as the external clock parameters are within the specified range. To
observe phase-lock connect oscilloscope probes to the input clock as well as to the SW
test point. Phase lock range can be determined by sweeping the external clock
frequency up / down until the device just goes out of lock at the two extremes of its
range.
For spread spectrum operation the input clock frequency may be swept between two
frequencies that are within the lock range. The sweep (jitter) repetition rate should be
limited to 10 kHz. The radiated EMI spectrum may be now measured in various states –
free running, phase locked to a fixed frequency and spread spectrum.
Before measuring radiated EMI, place a 10uF/0805, X7R capacitor at the input and
output edges of the PCB (C14 and C15), and connect the input power and the load to
the board at or near these capacitors.
The added capacitor at the input edge is for high-
frequency decoupling of the input cables. The one added at the output edge is meant to
represent a typical load decoupling capacitor.
GND
Ext. Clock
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