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Chapter 2: Board Components

2–13

FPGA Configuration

August 2017

Altera Corporation

Cyclone V GT FPGA Development Board

Reference Manual

FPGA Programming from Flash Memory

Flash memory programming is possible through a variety of methods. The default 
method is to use the factory design—Board Update Portal. This design is an 
embedded web server, which serves the Board Update Portal web page. The web 
page allows you to select new FPGA designs including hardware, software, or both in 
an industry-standard S-Record File (

.flash

) and write the design to the user hardware 

page (page 1) of the flash memory over the network.

The secondary method is to use the pre-built parallel flash loader (PFL) design 
included in the development kit. The development board implements the Altera PFL 
megafunction for flash memory programming. The PFL megafunction is a block of 
logic that is programmed into an Altera programmable logic device (FPGA or CPLD). 
The PFL functions as a utility for writing to a compatible flash memory device. This 
pre-built design contains the PFL megafunction that allows you to write either page 0, 
page 1, or other areas of flash memory over the USB interface using the Quartus II 
software. This method is used to restore the development board to its factory default 
settings.

Other methods to program the flash memory can be used as well, including the 
Nios

®

II processor. 

f

For more information on the Nios II processor, refer to the 

Nios II Processor

 page of 

the Altera website.

On either power-up or by pressing the program configuration push button, 

PGM_CONFIG

 (S5), the MAX V CPLD 5M2210 System Controller's PFL configures the 

FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash 
memory and converts it to fast passive parallel (FPP) format. This 8-bit data is then 
written to the dedicated configuration pins in the FPGA during configuration. 

Pressing the 

PGM_CONFIG

 push button (S5) loads the FPGA with a design page based 

on which 

PGM_LED[2:0]

 (D12, D13, D14) illuminates. You can select the design stored 

in the flash by pressing the 

PGM_SEL

 push button (S6) to cycle through the LEDs as 

defined in 

Table 2–6

.

Table 2–6

 lists the design that loads when you press the 

PGM_CONFIG

 push button. 

Table 2–6. PGM_LED Settings 

(1)

PGM_LED0 (D14)

PGM_LED1 (D13)

PGM_LED2 (D12)

Design

ON

OFF

OFF

Factory design

OFF

ON

OFF

User design 1

OFF

OFF

ON

User design 2

Note to 

Table 2–6

:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

Содержание Cyclone V GT FPGA

Страница 1: ...101 Innovation Drive San Jose CA 95134 www altera com MNL 01078 1 3 Reference Manual Cyclone V GT FPGA Development Board Feedback Subscribe Cyclone V GT FPGA Development Board Reference Manual...

Страница 2: ...products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no respo...

Страница 3: ...l USB Blaster 2 15 Status Elements 2 15 Setup Elements 2 17 Board Settings DIP Switch 2 17 JTAG Chain Control or PCI Express Control DIP Switch 2 18 FPGA Configuration Mode DIP Switch 2 18 CPU Reset P...

Страница 4: ...ly 2 50 Power Distribution System 2 51 Power Measurement 2 52 Chapter 3 Board Components Reference Compliance and Conformity Statements 3 3 Statement of China RoHS Compliance 3 3 CE EMI Conformity Cau...

Страница 5: ...ed mezzanine card HSMC connectors are available to add additional functionality via a variety of HSMCs available from Altera and various partners f To see a list of the latest HSMCs available or to do...

Страница 6: ...Quartus II Programmer MAX II CPLD EPM570ZM100 in a 100 pin MBGA package for use with ASSP optional Flash fast passive parallel FPP configuration Clocking circuitry Si570 and Si571 programmable oscill...

Страница 7: ...ernet LEDs One SDI carrier detect LED One power on LED One two line character LCD display Push buttons One CPU reset push button One MAX V reset push button One program select push button One program...

Страница 8: ...when touching the board Figure 1 1 Cyclone V GT FPGA Development Board Block Diagram ASSP CPLD SMA Clock Output Gigabit Ethernet PHY LCD DDR3 SMC x64 64 Optional SMA Differential Pair Clock Input DDR3...

Страница 9: ...iles for the development board reside in the Cyclone V GT FPGA development kit board design files directory f For information about powering up the board and installing the demonstration software refe...

Страница 10: ...ew of the Cyclone V GT FPGA Development Board Features Table 2 1 Board Components Part 1 of 4 Board Reference Type Description Featured Devices U13 FPGA Cyclone V GT 5CGTFD9E5F35C7N 1152 pin FBGA U32...

Страница 11: ...r to Table 2 6 for the LED settings D22 D23 D24 D25 D26 Ethernet LEDs Illuminates to show the connection speed as well as transmit or receive activity D32 SDI LEDs Illuminates to show the transmit or...

Страница 12: ...munication Ports J16 PCI Express edge connector Gold plated edge fingers connector for up to 4 signaling in Gen1 mode J1 J2 HSMC port Two ports one with four transceiver channels and 84 CMOS or 17 LVD...

Страница 13: ...age by function on the board SW2 Power switch Switch to power on or off the board when power is supplied from the DC input jack J15 Fan power Fan power header Table 2 1 Board Components Part 4 of 4 Bo...

Страница 14: ...wer measurement Control and status registers CSRs for remote system update SDI video port 2 5 V CMOS XCVR 6 Push buttons 1 5 V CMOS 4 DIP switches 1 5 V CMOS 8 Character LCD 1 5 V CMOS 2 LEDs 1 5 V CM...

Страница 15: ...oard Reference U32 Schematic Signal Name I O Standard Description L2 ASSP_CPLD_MRN 2 5 V For ASSP design optional R12 ASSP_MODE 2 5 V For ASSP design optional B9 CLK125_EN 2 5 V 125 MHz oscillator ena...

Страница 16: ...bus F13 FM_A8 1 8 V FM address bus E15 FM_A9 1 8 V FM address bus E16 FM_A10 1 8 V FM address bus F15 FM_A11 1 8 V FM address bus G14 FM_A12 1 8 V FM address bus F16 FM_A13 1 8 V FM address bus G13 F...

Страница 17: ..._CONFIG_D6 2 5 V FPGA configuration data E5 FPGA_CONFIG_D7 2 5 V FPGA configuration data F3 FPGA_CONFIG_D8 2 5 V FPGA configuration data E1 FPGA_CONFIG_D9 2 5 V FPGA configuration data F4 FPGA_CONFIG_...

Страница 18: ...nfiguration error LED A6 MAX_LOAD 2 5 V FPGA configuration active LED M10 MAX_OEN 1 8 V FM bus MAX V output enable M9 MAX_RESETN 1 8 V MAX V reset push button N10 MAX_WEN 1 8 V FM bus MAX V write enab...

Страница 19: ...header J13 FPGA Programming over Embedded USB Blaster This configuration method implements a type B mini USB connector J5 a USB 2 0 PHY device U4 and an Altera MAX II CPLD EPM570GT100C3N U49 to allow...

Страница 20: ...Z USB CY7C68013A device in a 56 pin VBGA package device is used to interface to a single type B mini USB connector This device has an on board 8051 CPU used in conjunction with embedded MAC logic to t...

Страница 21: ...of flash memory over the USB interface using the Quartus II software This method is used to restore the development board to its factory default settings Other methods to program the flash memory can...

Страница 22: ...ormation refer to Configuring the MAX V Device to Program EPCQ on page 2 11 Figure 2 4 PFL Configuration MAX V CPLD 5M2210 System Controller Cyclone V FPGA FPGA_DATA 15 0 FPGA_DCLK FLASH_A 26 1 FLASH_...

Страница 23: ...PGA Driven by the MAX V CPLD 5M2210 System Controller D5 MAX_ERROR 2 5 V Red LED Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA Driven by the MAX V CPLD 5M2210 Sy...

Страница 24: ...tes when HSMC port A has a board or cable plugged in such that pin 160 becomes grounded Driven by the add in card D2 HSMB_PRSNTn 3 3 V Green LED Illuminates when HSMC port B has a board or cable plugg...

Страница 25: ...nformation about the default settings of the DIP switches refer to the Cyclone V GT FPGA Development Kit User Guide Board Settings DIP Switch The board settings DIP switch SW4 controls various feature...

Страница 26: ...MAX V CPLD System Controller This push button is the default reset for both the FPGA and CPLD logic The MAX V CPLD 5M2210 System Controller also drives this push button during power on reset POR Tabl...

Страница 27: ...Valid settings include PGM_LED0 PGM_LED1 or PGM_LED2 on the three pages in flash memory reserved for FPGA designs Program Select Push Button The program select push button PGM_SEL S6 is an input to t...

Страница 28: ...A SMA CLK10 CLKINTOP_P N CLK5 CLK_125M_P N CLK6 CLKINA_50 CLK7 CLKIN_R_P N 50 MHz REFCLK_QL3_P N HSMB REFCLK_QL1_P N PCIe PCIE_REFCLK_P N CLK2 CLKINBOT_P N Buffer 100 MHz Default SMA 125 M Buffer 50 M...

Страница 29: ...QL3_P R11 Transceiver bank QL3 for HSMC port B transceivers REFCLK_QL3_N P10 SMA_CLKOUT_P Oscilloscope trigger output SMA_CLKOUT_N X3 REFCLK_QL2_P 148 500 MHz Programmable between 10 810 MHz LVDS U11...

Страница 30: ...VTTL inputs HSMB_CLK_IN_N1 LVDS LVTTL J25 HSMB_CLK_IN_P2 LVDS LVTTL J20 LVDS input from the installed HSMC cable or board Can also support 2x LVTTL inputs HSMB_CLK_IN_N2 LVDS LVTTL K19 PCI Express Edg...

Страница 31: ...n describes all user defined LEDs For information on board specific or status LEDs refer to Status Elements on page 2 15 General LEDs Board references D8 D11 and D15 D18 are eight user defined LEDs Th...

Страница 32: ...18 The LEDs are driven by the Cyclone V GT device Table 2 18 lists the PCI Express LED schematic signal names and their corresponding Cyclone V GT device pin numbers Table 2 16 General LED Schematic S...

Страница 33: ...ment board is designed to fit entirely into a PC motherboard with a 4 PCI Express slot that can accommodate a full height short form factor add in card This interface uses the Cyclone V GT s PCI Expre...

Страница 34: ...ing Logic HCSL Figure 2 6 shows the PCI Express reference clock levels The SMB connections are optional signals in the PCI Express specification The signals are wired to the Cyclone V GT device but ar...

Страница 35: ...V PCML Transmit bus A17 PCIE_TX_N0 AH3 1 5 V PCML Transmit bus A21 PCIE_TX_P1 AF4 1 5 V PCML Transmit bus A22 PCIE_TX_N1 AF3 1 5 V PCML Transmit bus A25 PCIE_TX_P2 AD4 1 5 V PCML Transmit bus A26 PCIE...

Страница 36: ...ENET_RX_D3 AK12 2 5 V CMOS RGMII receive data bus 94 ENET_RX_DV AH14 2 5 V CMOS RGMII receive data valid 11 ENET_TX_D0 AB14 2 5 V CMOS RGMII transmit data bus 12 ENET_TX_D1 AD15 2 5 V CMOS RGMII trans...

Страница 37: ...used for CMOS signaling 1 The HSMC is an Altera developed open specification which allows you to expand the functionality of the development board through the addition of daughtercards HSMCs f For mor...

Страница 38: ...V PCML Transceiver RX bit 3n 21 HSMA_TX_P2 T4 1 5 V PCML Transceiver TX bit 2 22 HSMA_RX_P2 U2 1 5 V PCML Transceiver RX bit 2 23 HSMA_TX_N2 T3 1 5 V PCML Transceiver TX bit 2n 24 HSMA_RX_N2 U1 1 5 V...

Страница 39: ...bit 4n or CMOS bit 23 77 HSMA_TX_D_P5 C13 LVDS or 2 5 V LVDS TX bit 5 or CMOS bit 24 78 HSMA_RX_D_P5 B8 LVDS or 2 5 V LVDS RX bit 5 or CMOS bit 25 79 HSMA_TX_D_N5 C12 LVDS or 2 5 V LVDS TX bit 5n or C...

Страница 40: ...SMA_TX_D_N13 E13 LVDS or 2 5 V LVDS TX bit 13n or CMOS bit 62 134 HSMA_RX_D_N13 B16 LVDS or 2 5 V LVDS RX bit 13n or CMOS bit 63 137 HSMA_TX_D_P14 A17 LVDS or 2 5 V LVDS TX bit 14 or CMOS bit 64 138 H...

Страница 41: ...JTAG_TCK AK5 2 5 V CMOS JTAG clock signal 36 HSMB_JTAG_TMS 2 5 V CMOS JTAG mode select signal 37 HSMB_JTAG_TDO 2 5 V CMOS JTAG data output 38 HSMB_JTAG_TDI 2 5 V CMOS JTAG data input 39 HSMB_CLK_OUT0...

Страница 42: ...MOS Memory data bus 131 HSMB_DQ26 G28 2 5 V CMOS Memory data bus 133 HSMB_DQ27 F25 2 5 V CMOS Memory data bus 137 HSMB_DQ28 G29 2 5 V CMOS Memory data bus 139 HSMB_DQ29 H24 2 5 V CMOS Memory data bus...

Страница 43: ...5 V CMOS Memory address bus 116 HSMB_A14 B20 2 5 V CMOS Memory address bus 126 HSMB_DM3 H27 2 5 V CMOS Data mask 128 HSMB_A15 A21 2 5 V CMOS Memory address bus 132 HSMB_BA0 B26 2 5 V CMOS Memory bank...

Страница 44: ...For more information about the application circuit of the cable driver refer to the cable driver data sheet in www national com Table 2 25 summarizes the SDI video output interface pin assignments sig...

Страница 45: ...d Table 2 27 summarizes the SDI video input interface pin assignments signal names and functions Table 2 26 SDI Cable Equalizer Lengths Data Rate Mbps Cable Type Maximum Cable Length m 270 Belden 1694...

Страница 46: ...e first 8 bits of the 8 device for ECC support DDR3B 64 bit interface using a soft memory controller This data bus consists of four 16 devices DDR3A The DDR3A SDRAM comprises of three 16 devices with...

Страница 47: ...Write mask byte lane E3 DDR3A_DQ0 AN19 1 5 V SSTL Class I Data bus byte lane 0 F7 DDR3A_DQ1 AM19 1 5 V SSTL Class I Data bus byte lane 0 F2 DDR3A_DQ2 AP20 1 5 V SSTL Class I Data bus byte lane 0 F8 DD...

Страница 48: ...s R3 DDR3A_A9 AJ16 1 5 V SSTL Class I Address bus L7 DDR3A_A10 AL16 1 5 V SSTL Class I Address bus R7 DDR3A_A11 AM16 1 5 V SSTL Class I Address bus N7 DDR3A_A12 AM13 1 5 V SSTL Class I Address bus T3...

Страница 49: ...Data strobe N byte lane 2 C7 DDR3A_DQS_P3 Y20 Differential 1 5 V SSTL Class I Data strobe P byte lane 3 B7 DDR3A_DQS_N3 AA20 Differential 1 5 V SSTL Class I Data strobe N byte lane 3 K1 DDR3A_ODT AN21...

Страница 50: ...F7 DDR3A_DQ33 AG23 1 5 V SSTL Class I Data bus byte lane 4 F2 DDR3A_DQ34 AN32 1 5 V SSTL Class I Data bus byte lane 4 F8 DDR3A_DQ35 AN29 1 5 V SSTL Class I Data bus byte lane 4 H3 DDR3A_DQ36 AK25 1 5...

Страница 51: ...STL Class I Address bus P2 DDR3B_A5 R33 1 5 V SSTL Class I Address bus R8 DDR3B_A6 N32 1 5 V SSTL Class I Address bus R2 DDR3B_A7 G33 1 5 V SSTL Class I Address bus T8 DDR3B_A8 AE34 1 5 V SSTL Class I...

Страница 52: ...Data strobe N byte lane 0 C7 DDR3B_DQS_P1 W29 Differential 1 5 V SSTL Class I Data strobe P byte lane 1 B7 DDR3B_DQS_N1 W30 Differential 1 5 V SSTL Class I Data strobe N byte lane 1 K1 DDR3B_ODT AA32...

Страница 53: ...Class I Data bus byte lane 2 H8 DDR3B_DQ21 V32 1 5 V SSTL Class I Data bus byte lane 2 G2 DDR3B_DQ22 AH34 1 5 V SSTL Class I Data bus byte lane 2 H7 DDR3B_DQ23 W32 1 5 V SSTL Class I Data bus byte lan...

Страница 54: ...9 1 5 V SSTL Class I Bank address bus M3 DDR3B_BA2 P27 1 5 V SSTL Class I Bank address bus K3 DDR3B_CASN N27 1 5 V SSTL Class I Row address select K9 DDR3B_CKE AF32 1 5 V SSTL Class I Column address s...

Страница 55: ...L Class I Reset L3 DDR3B_WEN AM34 1 5 V SSTL Class I Write enable L8 DDR3B_ZQ03 1 5 V SSTL Class I ZQ impedance calibration DDR3 x16 U15 N3 DDR3B_A0 H29 1 5 V SSTL Class I Address bus P7 DDR3B_A1 K28...

Страница 56: ...ass I Data bus byte lane 7 C3 DDR3B_DQ57 K29 1 5 V SSTL Class I Data bus byte lane 7 C8 DDR3B_DQ58 G31 1 5 V SSTL Class I Data bus byte lane 7 C2 DDR3B_DQ59 M30 1 5 V SSTL Class I Data bus byte lane 7...

Страница 57: ...al Names and Functions Part 1 of 2 Board Reference U20 Schematic Signal Name Cyclone V GT Pin Number I O Standard Description F6 FLASH_ADVN AB34 2 5 V Address valid B4 FLASH_CEN AA21 2 5 V Chip enable...

Страница 58: ...Address bus B8 FSM_A26 AD24 2 5 V Address bus F2 FSM_D0 AJ31 2 5 V Data bus E2 FSM_D1 AA23 2 5 V Data bus G3 FSM_D2 Y23 2 5 V Data bus E4 FSM_D3 Y22 2 5 V Data bus E5 FSM_D4 W24 2 5 V Data bus G5 FSM...

Страница 59: ...V 3 067 A 2 5 V 7 199 A 2 5V EMP2210 VCCIO1 2 ENET VDD Oscillators Clock Buffers 2 5 V 1 065 A 1 8V EPM2210 VCCINT and VCCIO3 4 Flash VDD VDDQ EMP540 VCCINT Oscillator 50 MHz 1 8 V 0 256 A LTC3022 1...

Страница 60: ...il Figure 2 11 Power Measurement Circuit SCK SPI Bus DSI DSO CSn 8 Ch Power Supply Load 0 7 RSENSE MAX V CPLD 5M2210 System Controller Cyclone V GX FPGA To User PC JTAG Chain Feedback 14 pin 2x16 Char...

Страница 61: ...YW TR www lumex com D5 Red LED Lumex Inc SML LXT0805IW TR www lumex com D21 Blue LED Lumex Inc SML LX0805USBC TR www lumex com SW3 SW4 Four position DIP switch C K Components ITT Industries TDA04H0SB1...

Страница 62: ...e driver with cable detect National Semiconductor LMH0303SQx www national com U47 3 Gbps HD SD SDI adaptive cable equalizer National Semiconductor LMH0384SQ www national com U8 U15 U22 U26 U27 U28 U30...

Страница 63: ...EMI caused as the result of modifications to the delivered material is the responsibility of the user Table 3 2 Table of Hazardous Substances Name and Concentration Notes 1 2 Part Name Lead Pb Cadmiu...

Страница 64: ...3 4 Chapter 3 Board Components Reference Compliance and Conformity Statements Cyclone V GT FPGA Development Board August 2017 Altera Corporation Reference Manual...

Страница 65: ...REFCLK_P June 2013 1 0 Initial release Contact 1 Contact Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Pr...

Страница 66: ...yword SUBDESIGN and logic function names for example TRI r An angled arrow instructs you to press the Enter key 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of t...

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