Altera Cyclone III FPGA, Справочное руководство

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2–6 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Clocking Circuitry
Table 2–3 lists the Cyclone III EP3C25F324 device pin count.
You can configure the Cyclone III device via the on-board USB-Blaster
™
or
through the JTAG interface using an external programming cable (sold
separately).
f
For additional information about Altera devices, go to
www.altera.com/products/devices .
Clocking
Circuitry
The Cyclone III FPGA starter board’s clocking circuitry is designed to be
simple and easy to use. A single 50-MHz clock input is used and all other
clocks are generated using the Cyclone III device’s phase-locked loops
(PLLs). The dedicated PLLs are used to distribute the flash, SSRAM, and
HSMC clocks.
Table 2–4 shows the clock pinout.
Table 2–3. Cyclone III Device Pin Count
Board Component Pins
SRAM/flash (shared bus) 72
SDRAM (DDR) 42
Push buttons 4
LEDs 4
USB-Blaster/configuration 4
HSMC 84
Total Pins Used 210
Total EP3C25F324 pins 214
Unused pins 4 (1)
Note to Table 2–3 :
(1) In some DDR designs, you will be unable to use some of the other I/Os that share
the same VREF banks with the DDR. Therefore, if you have added DDR to your
system, you will need to remove two or three LEDs or I/Os for the HSMC
connector, which shares the same VREF bank as the DDR.
Table 2–4. Clock Pinout
Signal Name FPGA Pin Direction Type
50MHz B9 Input 2.5 V