8–6
Chapter 8: Reset and Clocks
Clocks
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
The CDC module implements the asynchronous clock domain crossing between the
PHY/MAC
pclk
domain and the Data Link Layer
coreclk
domain. The transceiver
pclk
clock is connected directly to the Hard IP for PCI Express and does not connect
to the FPGA fabric.
coreclkout
The
coreclkout
signal is derived from
pclk
.
lists frequencies for
coreclkout
, which are a function of the link width, data rate, and the width of the
Avalon-ST bus.
The frequencies and widths specified in
are maintained throughout
operation. If the link downtrains to a lesser link width or changes to a different
maximum link rate, it maintains the frequencies it was originally configured for as
specified in
. (The Hard IP throttles the interface to achieve a lower
throughput.)
pld_clk
coreclkout_hip
can drive the Application Layer clock along with the
pld_clk
input
to the Arria V GZ V Hard IP for PCI Express IP Core. The
pld_clk
can optionally be
sourced by a different clock than coreclkout_hip. The
pld_clk
minimum frequency
cannot be lower than the
coreclkout_hip
frequency. Based on specific Application
Layer constraints, a PLL can be used to derive the desired frequency.
Table 8–3. coreclkout_hip Values for All Parameterizations
Link Width
Max Link Rate
coreclkout_hip
×1
Gen1 64
125
MHz
×1
Gen1
64
62.5 MHz
×2
Gen1
64
125 MHz
×4
Gen1 64
125
MHz
×8
Gen1 64
250
MHz
×8
Gen1
128
125 MHz
×1
Gen2
64
125 MHz
×2
Gen2
64
125 MHz
×4
Gen2
64
250 MHz
×4
Gen2
128
125 MHz
×8
Gen2
128
250 MHz
×8
Gen2
256
125 MHz
×1
Gen3
64
125 MHz
×2
Gen3
64
250 MHz
×2
Gen3
128
125 MHz
×4
Gen3
128
250 MHz
×4
Gen3
256
125 MHz
×8
Gen3
256
250 MHz
:
(1) The 256-bit interface is only available for the Avalon-ST interface.
(2) This mode saves power.