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Altera Arria GX, Справочное руководство

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2–28

Reference Manual

Altera Corporation

Arria GX Development Board

October 2007

Standard Communication Ports

Figure 2–8. Example Mezzanine Cards

JTAG Interface

The board provides a right-angle, 10-pin JTAG header. The JTAG header 
protrudes through the front panel of the PCIe card, which positions it well 
for internal accessibility while the box is closed. Pin 1 is located on the 
side nearest the SFP connectors.

The JTAG header can be used for JTAG-based FPGA programming as 
well as communication to a standard computer using a USB-Blaster 
download cable. The default USB-Blaster driver that Quartus II software 
installs for JTAG programming and SignalTap debugging.

f

For more information on the JTAG chain, refer to 

“JTAG Chain 

Configuration” on page 2–9

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Содержание Arria GX

Страница 1: ...101 Innovation Drive San Jose CA 95134 www altera com Arria GX Development Board Reference Manual Document Date October 2007...

Страница 2: ...ights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and servi...

Страница 3: ...n Configuration 2 9 Flash Memory Configuration 2 11 MAX II CPLD Configuration Controller 2 13 Configuration Push Button S5 2 14 Clocking Circuitry 2 15 General User Interfaces 2 17 Push Button Switche...

Страница 4: ...iv Altera Corporation Preliminary Contents Stratix Device Handbook Volume 1...

Страница 5: ...mation about Altera products refer to the following table Chapter Date Version Changes Made 1 October 2007 1 0 0 First publication Information Type Contact Note 1 Technical support www altera com mysu...

Страница 6: ...References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courie...

Страница 7: ...eed low latency memory access via a DDR2 SDRAM memory interface the Arria GX development board provides a fully integrated solution for multi channel high performance applications while also using lim...

Страница 8: ...the following component blocks 780 pin Altera Arria GX EP1AGX60 FPGA 60K logic elements LEs Eight transceiver channels 128 18 X 18 multiplier blocks Four phase locked loops PLLs 395 user I Os Transcei...

Страница 9: ...ration push button Two general user push buttons DIP switches One user DIP switch One configuration DIP switch Two slider switches for JTAG chain control Power supply PCI Express power input External...

Страница 10: ...handling the board it is important to observe the following precaution c Static Discharge Precaution Without proper anti static handling the board can be damaged Therefore use anti static handling pre...

Страница 11: ...sections Featured device Configuration Clocking circuitry User interface components Off chip memory Standard communication ports Power supply Temperature sensor Heat sink and fan 1 A complete set of...

Страница 12: ...nt board Figure 2 1 Top View of the Arria GX Development Board 3 ONNECTOR 0OWER ACK 0OWER 3WITCH 37 5SER 0 3WITCH 3 5SER 0USH UTTON 3WITCHES 3 3 3 ONFIGURATION ONE ONFIGURATION 0USH UTTON 3 ONFIGURATI...

Страница 13: ...ort A D11 Power LED Blue LED indicates when power is applied to the board D21 D22 D23 Voltage present LEDs Green LEDs that indicate the presence of 1 5 V 2 5 V and 1 2 V power S5 Configuration push bu...

Страница 14: ...tion of HSMC daughter cards Power J1 DC power jack DC input connector for the board SW1 Power switch 1 Slide switch that enables power to the board Note to Table 2 1 1 Power switch is bypassed when th...

Страница 15: ...P1AGX60DF780 device Figure 2 2 Arria GX Device I O Mapping Resources Figure 2 3 illustrates the clocking resources for the EP1AGX60DF780 device The parenthetical text refers to board level signals as...

Страница 16: ...D and a 16 bit page mode flash memory device The 512 Mb flash memory device can hold eight designs where each design is 16 951 824 bits in size for the EP1AGX60DF780 device plus 32 MBytes for other st...

Страница 17: ...ption Manufacturer Manufacturer Part Number Manufacturer Web Site U5 MAX II CPLD Altera EPM570F100C5N www altera com U6 512 Mbit flash memory Spansion LLC S29GL512N www spansion com J6 JTAG connector...

Страница 18: ...uration DIP switch ONFIGURATION 0 3WITCH 30 3 B 3 6 7 7 6 3 3 3 N 3 N 3 7 N 3 70N 3 2 3 4N 3 94 N 3 29 39N 0 0 0 0 N 3 3 3 3 34 453N 8 0 2 8 0 8 8 4 N 25 5 0 0 037 0 037 0 037 0 3 3 3 3 N 3 N 3 7 N 3...

Страница 19: ...Arria GX device and optionally the MAX II CPLD as well as the HSMC expansion connector The MAX II and HSMC slots are by passable so that devices on the mezzanine card can be optionally addressed thro...

Страница 20: ...g Altera devices refer to the Altera Configuration Handbook 3 4 EADER 4 4 3 4 4 0 4 8 4 8 4 37 6 6 4 4 3 4 6 4 6 8 0 37 0 4 22 8 0 6 Table 2 5 JTAG Chain I O Signals Note 1 Signal Name Description JTA...

Страница 21: ...and a USB Blaster cable This is done via the JTAG header and the MAX II CPLD to flash memory Table 2 6 lists an example flash memory map The sizes of various blocks may change based on the settings us...

Страница 22: ...in Numbers Schematic Signal Name Description Signal Type K2 K3 H4 J4 K4 J5 K5 K6 J6 K7 K8 H7 J8 H8 K10 J9 H9 J10 H10 G8 G9 G10 F10 F9 FLASH_A 24 0 Address bus 3 3 V CMOS out 25 bit C2 B1 C1 D3 D2 D1 E...

Страница 23: ...MAX II CPLD as far as direction and signaling standard Table 2 9 Flash Memory Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufa...

Страница 24: ...ASH_WEn Flash write enable 3 3 V CMOS out A1 B2 CONFIG_MODE 1 0 Configuration mode input 3 3 V CMOS in A3 A2 B3 C3 MSEL 3 0 FPGA mode select output 3 3 V CMOS out E2 MAX_EN Enables operation for PFL 3...

Страница 25: ...er See Configuration DIP Switch S6 on page 2 19 The 62 5 MHz and 125 MHz oscillators ensure that all protocols supported by the Arria GX device are provided for Table 2 11 lists the Arria GX developme...

Страница 26: ...LK OUPLED OUPLED OUPLED OUPLED RRIA 8 2EFCLK NPUT 8 ONFIGURATION ONTROLLER RRIA 8 NHANCED NPUTS Table 2 12 Arria GX Development Board Clock Distribution Part 1 of 2 Source Schematic Signal Name I O St...

Страница 27: ...special label is intended to encourage its use as a logic reset signal for FPGA designs so that user designs are reset in a consistent manner 1 All push buttons are a logic 1 until depressed Table 2...

Страница 28: ...nput control Each pin can be set to a logic 0 by setting it to the closed position and each pin can be set to logic 1 by setting it to the open position Table 2 14 lists the DIP switch settings schema...

Страница 29: ...driven to a logic 1 Table 2 16 shows the configuration DIP switch S6 signal names and descriptions Table 2 15 User Defined LED Pin Out Board Reference Schematic Signal Name Arria GX Device Pin Number...

Страница 30: ...icate successful configuration power on status connection to the HSMC expansion connector etc Tables 2 18 lists the board status LEDs CLK_SEL0 Local oscillator SMA input select on local oscillator C7...

Страница 31: ...ow two per channel Table 2 20 DDR2 Description Signal Type Schematic Signal Name Arria GX Pin Number Part 1 of 2 Description Signal Type Schematic Signal Name Arria GX Pin Number Address row and colum...

Страница 32: ...1 8 V VDD N A 1 I O supply 1 8 V VDDQ N A 1 DLL supply 1 8 V VDDL N A 1 Core GND Ground VSS N A 1 I O GND Ground VSSQ N A 1 DLL GND Ground VSSL N A 1 Notes to Table 2 20 1 This is a power pin that is...

Страница 33: ...o operate in the PCIe x1 mode The PCIe signals have differential traces terminated on the receive side using internal termination resistors in the Arria GX device receiver pins Table 2 22 lists the PC...

Страница 34: ...limited transceiver resources four transceiver channels route to the HSMC interface f For more information about the Altera HSMC interface refer to the HSMC specifications on the Altera website www a...

Страница 35: ...V LVCMOS in out 17 bits or LVDS 17 TX channels n HSMA_TX_D_N 16 0 F23 E25 G23 H22 J23 G25 H25 J24 K25 M24 P24 Y24 AA25 AA22 AB21 AB23 AC24 2 5 V LVCMOS in out 17 bits or LVDS 17 RX channels p HSMA_RX...

Страница 36: ...layout style Management serial data line 2 5 V LVCMOS in out HSMA_SDA A20 Management serial clock line 2 5 V LVCMOS out HSMA_SCL A18 JTAG clock N A part of chain JTAG_TCK V17 JTAG mode select N A part...

Страница 37: ...Connector For illustration purposes Figure 2 8 shows example mezzanine cards The top left is a x8 PCIe female adapter right angle and the top right is an AMC header type B adapter The lower two figure...

Страница 38: ...Pin 1 is located on the side nearest the SFP connectors The JTAG header can be used for JTAG based FPGA programming as well as communication to a standard computer using a USB Blaster download cable T...

Страница 39: ...Similarly the 12 V HSMC power can be supplied from the DC input jack 12V_SWITCHER or from a 12 V connection supplied by a PC 12V_PC_CONN Figure 2 9 shows the power distribution system Figure 2 9 Arri...

Страница 40: ...face to a National Semiconductor temperature sensing device LM95235 which is a low bandwidth A D converter that measures small voltage changes across a temperature diode on the die of the Arria GX dev...

Страница 41: ...Components Heat Sink and Fan The Dynatron SCP1 heat sink unit provides heat dissipation for the Arria GX device The fan uses 190mA at 12 V and can dissipate 25 W of heat with no additional air flow i...

Страница 42: ...2 32 Reference Manual Altera Corporation Arria GX Development Board October 2007 Heat Sink and Fan...

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