Altera Arria 10 SoC Скачать руководство пользователя страница 25

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Controls

Description

Factory Test Version

Indicates the version of the Board Test System currently running on
the board.

JTAG Chain

Shows all the devices currently in the JTAG chain.

Qsys Memory Map

Shows the memory map of the Qsys system on your board.

4-6

The System Info Tab

UG-20004

2016.03.01

Altera Corporation

Board Test System

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Содержание Arria 10 SoC

Страница 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Страница 2: ...Arria 10 SoC Development Kit User Guide Subscribe Send Feedback UG 20004 2016 03 01 101 Innovation Drive San Jose CA 95134 www altera com...

Страница 3: ...r Driver 2 5 SD Card Image with Example Software 2 5 Development Board Setup 3 1 Applying Power to the Board 3 1 Default Switch and Jumper Settings 3 2 Board Test System 4 1 Preparing the Board 4 2 Ru...

Страница 4: ...try 5 23 On Board Oscillators 5 23 Components and Interfaces 5 24 PCI Express 5 24 10 100 1000 Ethernet HPS 5 26 10 100 1000 Ethernet FPGA 5 28 FMC 5 29 HPS Shared I O 5 44 USB 2 0 Port HPS 5 46 RS 23...

Страница 5: ...ernet FPGA Ethernet FMCB PCIE EP I O MAX V CPLD x2 2016 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Alt...

Страница 6: ...d Reset FMC B Daughtercard Port FMC A Daughtercard Port USB UART FPGA HPS_DP 0 3 Trace x16 12V AC Adapter USB Blaster II JTAG Header RS232 UART MAX V CPLD System Controller FPGA_PB 0 3 HPS_PB 0 3 HPS_...

Страница 7: ...oscillator for SDI interface Supported Memory HPS memory size HiLO card 2GB DDR3 256Mb x 40 x dual rank 1GB DDR3 256Mb x 40 x single rank 1GB DDR4 256Mb x 40 x single rank ships with kit FPGA memory...

Страница 8: ...V57 1 High Pin Count FMC slot FPGA Altera Low Pin Count FMC slot FMC_PCIe Gen2 x8 EP cable FPGA PCIe GEN1 2 3 x8 RC slot FPGA Communication ports 2x SGMII Gigabit Ethernet ports PHY PN 88E1111 B2 NDC...

Страница 9: ...control DIP switch Board settings DIP switch FPGA configuration mode DIP switch General user DIP switch Power supply 12V DC Input Mechanical 7 175 x 9 3 rectangular form factor Recommended Operating C...

Страница 10: ...used for developing hardware and software for Altera devices 2016 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are tradem...

Страница 11: ...a development tools download the Quartus Prime Pro Edition Software from the Quartus Prime Pro Edition page in the Download Center of the Altera website Related Information Quartus Prime Software page...

Страница 12: ...r your development kit serial number and click Search 6 When your product appears turn on the check box next to the product name 7 Click Activate Selected Products and click Close 8 When licensing is...

Страница 13: ...The installation program creates the development kit directory structure shown in the following figure Figure 2 1 Installed Development Kit Directory Structure install dir documents board_design_files...

Страница 14: ...n the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions Related I...

Страница 15: ...s configured successfully 2016 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and regis...

Страница 16: ...J3 J5 J4 J7 1 2 3 4 ON SW4 Note The Switch position is represented by the black box To restore the switches to their factory default settings perform these steps 1 Set the DIP switch bank SW1 to matc...

Страница 17: ...Bit Name Bit Function Default Position 1 Reserved Reserved OFF 2 MSEL0 Switch 4 2 has the following options ON Up MSEL0 is 1 OFF Down MSEL0 is 0 OFF 3 MSEL1 Switch 4 3 has the following options ON Up...

Страница 18: ...OFF MAX V JTAG Enable OFF 3 FMCA ON FMCA JTAG Bypass OFF FMCA JTAG Enable ON 4 FMCB ON FMCB JTAG Bypass OFF FMCB JTAG Enable ON 5 PCIe ON PCIe JTAG Bypass OFF PCIe JTAG Enable ON 6 MSTR0 On Board USB...

Страница 19: ...35 V SHORT 7 and 8 1 5 V SHORT 9 and 10 1 8 V SHORT 9 and 10 J42 Voltage of FMCAVADJ No SHORT 1 1 V SHORT 1 and 2 1 1 V SHORT 3 and 4 1 2 V SHORT 5 and 6 1 35 V SHORT 7 and 8 1 5 V SHORT 9 and 10 1 8...

Страница 20: ...are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Al...

Страница 21: ...onitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Note Because the BTS is designed based on the Quartus Prime Programmer and syst...

Страница 22: ...Quartus Prime software s specific library Before running the BTS open the Quartus Prime software to automatically set the environment variable QUARTUS_ROOTDIR The Board Test System uses this environme...

Страница 23: ...ding tabs become active for testing Figure 4 2 The Configure Menu To configure the FPGA with a test system design perform the following steps 1 On the Configure menu click the configure command that c...

Страница 24: ...ription Board Information The board information is updated once the GPIO design is configured Otherwise this control displays the default static information about your board Board Name Indicates the o...

Страница 25: ...ard Test System currently running on the board JTAG Chain Shows all the devices currently in the JTAG chain Qsys Memory Map Shows the memory map of the Qsys system on your board 4 6 The System Info Ta...

Страница 26: ...O Tab User DIP Switch Displays the current positions of the switches in the user DIP switch bank SW2 Change the switches on the board to see the graphical display change accordingly User LEDs Displays...

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