CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 6
Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
2.
HOST (CPCI) SIDE
2.1 CPCI CONFIGURATION REGISTERS
The card presents the following configuration values to the CPCI system, based on the
values stored in the NVRAM device read by the AMCC PCI interface chip.
Register
Value (Meaning)
Vendor ID
0x13c5 (ALPHI Technology)
Device ID
0x0201 (CPCI-QIPC)
Revision ID
0x00
Class Code
0xff0000 (Device does not fit into defined class codes)
Interrupt Line
0xff
Interrupt Pin
A
Multifunction Device
No
Build In Self Test
No
Latency Timer
0x00
Minimum Grant
0x00
Maximum Latency
0x00
Expansion ROM Size
None
Table 2.1: PCI Configuration Registers
2.2 CPCI BASE ADDRESS REGISTERS
The card requests base address regions from the CPCI system after RESET, based on the
values stored in the NVRAM device read by the AMCC PCI interface chip.
The decode addresses of these regions are assigned by the host processor. The
CPCI-
QIPC
uses 3 of the 5 AMCC mapped base address registers. The AMCC is normally
programmed at the factory to request the following resources from the CPCI BIOS:
BASE
BAR
From
To
Description
Type
0
0x00000000
0x00000003F
AMCC PCI Operation Registers
MEM
1
0x00000000
0x00FFFFFF
Reserved for future use
MEM
3
0x00000000
0x003FFFFF
Dual Port Memory
MEM
3
0x00400000
0x01FFFFFF
Reserved for future use
MEM
Table 2.2: Base Addresses and Use
NOTE: The AMCC has been programmed to request memory above 1 Mbytes.
2.3 CPCI OPERATION REGISTERS
The host processor communicates with the
CPCI-QIPC
module via the AMCC pass-through
interface. After the base address registers have been programmed by the CPCI
configurator, incoming CPCI I/O or Memory cycles are translated into either accesses to the
