Alpha Data ADM-XRC-7Z2, Руководство пользователя

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ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
The following voltage rails and temperatures are monitored by the microcontroller:
Monitor Purpose
VPWR Board Input Supply (either 5.0V or 12.0V)
12V0 12V Board Input Supply
5V0 5V Board Input Supply
3V3 Board Input Supply
2V5 FPGA IO Supply
AUX_IO_2V0 FPGA Aux IO Supply
1V8 FPGA Aux Supply, Flash Memory
MGT_AUX_1V8 FPGA MGT Aux Supply
1V5 DDR3 SDRAM, Target FPGA memory I/O
1V0 FPGA Core Supply (VccINT)
MGT_1V2 FPGA MGT Vtt Supply
MGT_1V0 FPGA MGT Vcc Supply
3V3_INT Internal 3.3V Supply
Temp1 microcontroller internal temperature
Temp2 TMP422 internal temperature
Temp3 FPGA on-die temperature (measured in TMP422)
Table 17 : Voltage and Temperature Monitors (in microcontroller)
The SDK includes an example application ("monitor") that reads the system monitor sensor values.
4.9.1 Automatic Temperature Monitoring
The system monitor checks that the board and FPGA are being operated within the specified limits. If the
temperature is close to the limit, a "Warning Alarm" interrupt is set.
If a limit is exceeded, a "Critical Alarm" interrupt is set. After the Critical Alarm is set, there is a 5 second delay
before the system monitor unconfigures the FPGA by asserting its "PROG" pin.
The purpose of this mechanism is to protect the card from damage due to over-temperature. It is possible that it
will cause the user application and, possibly, the host computer to "hang".
The temperature limits are shown in Table Temperature Limits. Note that the Min and Max values include a 5°C
margin to prevent measurement errors triggering a false alarm.
.
Target FPGA Board (uC and PCB)
Min
Lower
Warning Upper
Warning
Max Min
Lower
Warning Upper
Warning
Max
Commercial -5°C +5°C +80°C +90°C -5°C +5°C +65°C +75°C
Extended -5°C +5°C +95°C +105°C -5°C +5°C +80°C +90°C
Industrial -45°C -35°C +95°C +105°C -45°C -35°C +80°C +90°C
Table 18 : Temperature Limits
4.9.2 System Monitor Status LEDs
LEDs D5 (Green) and D6 (Red) indicate the microcontroller status.
Page 16 Functional Description
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