ADM-VPX3-9Z5-RTM User Manual
V1.0 - 8th June 2021
3.4 LED Definitions
The position and description of the board status LED is shown in
:
D3
D4 D5
Figure 4 : LED Locations
Comp. Ref.
Function
ON State
Off State
D3(Green)
Display Port 3.3V Supply Status
Normal operation
Fault
D4(Green)
PSMIO31 LED
PSMIO=Logic Low
PSMIO=Logic High
D5(Green)
3.3V Supply Status
Normal operation
Power Off
Table 3 : LED Definitions
3.5 JTAG Interface
3.5.1 On-board Interface
The JTAG boundary scan chain can be accessed via a standard header (J11).
This allows the connection of the Xilinx JTAG cable for FPGA debug and Flash programming via the Xilinx
toolchain.
3.5.2 JTAG Voltages
The Vcc supply provided to the JTAG cable on the config header is +3.3V and is protected by a poly fuse rated at
350mA.
Page 7
Functional Description
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