ADM-VPX3-9Z5-RTM User Manual
V1.0 - 8th June 2021
Pin
Signal Name
FPGA Pin
1
P1_GP_1V8_P_12
BB5
2
P1_GP_1V8_P_11
AV12
3
P1_GP_1V8_N_12
BB4
4
P1_GP_1V8_N_11
AW12
5
GP8_1V8_P
AM11
6
GP7_1V8_P
AM10
7
GP8_1V8_N
AN11
8
GP7_1V8_N
AN10
9
GP6_1V8_P
AL15
10
GP5_1V8_P
AL14
11
GP6_1V8_N
AM15
12
GP5_1V8_N
AM14
Table 9 : Header J2
Pin
Signal Name
FPGA Pin
1
GP_SE_3V3_5
D2
2
GP_SE_3V3_2
C3
3
GP_SE_3V3_4
C5
4
GP_SE_3V3_3
C6
5
GP_SE_3V3_6
C1
6
GP_SE_3V3_1
C4
7
GP_SE_3V3_7
D4
8
GP_SE_3V3_0
B1
Table 10 : Header J15
Page 10
Functional Description
ad-ug-1392_v1_0.pdf