Allis-Chalmers MA-150, Инструкция

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SCR
TYPICAL RESET
AELAY CIRCUIT
A constant voltage Vc is maintained across the terminals AB by the
two zener diodes
OJ
and
02.
Resistor Rd drops the supply voltage to
a value above the diode control voltage and the diodes further reduce
the voltage to the control voltage value, Vc. The control voltage Vc
causes the diodes to conduct and an increase or decrease in supply
voltage wil
I
produce a corresponding change in the current which
causes a change in the voltage drop across Rd equal to the change in
supply voltage. To summarize, an increase or decrease in supply
voltage wil
I
not affect the constant voltage drop Vc across the
diodes. Two diodes in series are used because they provide more
precise voltage regulation than one diode.
The unijunction'transistor (UJT) is a switch which when turned on
wi
I I
allow a short pulse of relatively high current to flow and wil
I
then shut off. The terminals EB J ,of the UJT are an open circuit
until the voltage at E exceeds a precise level VF. I n other words
the UJT does not allow current to flow from point E to point B J until
the UJT is turned on by the fi.ring voltage VF· The voltage drop Vc
across the terminals AB charges the capacitor C J through the variable
resistor RJ· The time that it takes the capacitor
c1
to charge to
the firing voltage (VF) of the UJT is the time delay, and is control led
by the variable
resistor R]
R
1
is preset in the factory for a de
I
ay of ten eye
I
es and
I
ocked in
place by the stem locking nut.
A 5°
change in resistor setting would
mean a change in delay of approximately
1/2
cycle. The unit is
adjustable from an approximately instantaneous to a
60
cycle delay.
Any readjustment should be made using a cycle counter or equivalent
for ·timing.
When the voltage drop across the. capacitor and therefore at point E,
exceeds VF the terminals EB J,act as a short circuit and the UJT
discharges the capacitor through R2 and the gate terminal of the
silicon controlled rectifier (SCR). That is, the UJT allows current
to flow from the capacitor at point E to point
s1
and into the gate
terminal of the SCR.
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