Publication 2364F-5.05 - March 1999
A-10
Reference Information
Firmware Diagrams
Figure 5
Firmware Block Diagram–Regulation
B us Prefil Fdbk
140
S caled B us Fbk
143
B ase D C B u s Volt
1 6
B u s Volt C al
14 4
S im B us F db k
21 8
2 19
Feedback Select
21 6
S im ulator L oa d
21 5
S im ulator R ate
21 7
S im ulator p u C a p
iq R eference
(96 )
13 9
B us Volt in S el
14 B it A /D C han2
(38 )
D S P D C B us
(60 )
D S P avg D C B us
(61 )
13 8
Leadlag G ain, kn
1 37
Leadlag Freq, w n
130
A utoR ef Tracking
B ase D C B u s Volt
(1 6)
N om Line Voltage
(1 0)
Line Voltage
(14 )
20 7
B us Volt C m d
12 3
Volt M ode S el
1 22
A ux Volt Cm d
B u s R ef A uto
12 9
1 24
M in B us R ef
125
M ax B us R ef
B u s R ate R ef
12 6
R ef C hange R ate
12 7
B us R eferen ce
12 8
B us Feedback
1 41
B u s R ate
(4 096= B ase D C B us Volt)
R ef Lim it
C alculator
Feedback
S caling
kn
2 56
S + w n
S + w n
S im ulator
1/4
1/4
0
1
2
0
1
2
3
M ax
M in
1
0