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FPGA Video Processing Development Platform AV6150 User Manual 

 

  16 / 55

 

 

 

Contact Email: [email protected] 

 

In addition, the normal operation of DDR3 requires DDR3 address line and 

control  line  to  provide  termination  voltage  VTT  and  DDR3  chip  reference 
voltage  VREF,  VTT  and  VREF  voltage  are  both  0.75V,  the  following  Figure 
3-3-2 is the power part schematic. 
 

 

Figure 3-3-2: DDR3 Power for VTT/VREF 

 

 

Figure 3-3-3: DDR3 Power Circuit on the FPGA Board 

Содержание AV6150

Страница 1: ...FPGA Video Processing Development Platform AV6150 User Manual...

Страница 2: ...PGA Video Processing Development Platform AV6150 User Manual 2 55 Contact Email rachel zhou alinx com cn Version Record Version Date Release By Description Rev 1 0 2019 05 01 Rachel Zhou First Release...

Страница 3: ...AM 15 Part 3 4 SPI Flash 17 Part 3 5 Crystal oscillator on Core Board 19 Part 3 6 LED Light on Core Board 20 Part 3 7 AV6150 Power Supply 22 Part 3 8 Powe interface on Core Board 24 Part 3 9 Expansion...

Страница 4: ...FPGA Video Processing Development Platform AV6150 User Manual 4 55 Contact Email rachel zhou alinx com cn Part 4 10 JTAG Interface 52 Part 4 11 Buttons 53 Part 4 12 Power Supply 54...

Страница 5: ...ny s ALTERA video development board In terms of hardware design we added HDMI input Gigabit Ethernet CMOS Camera interface and Micro SD card slot This greatly enriches the functions of the video image...

Страница 6: ...core algorithm of video image processing fully utilizes the parallel processing capability of FPGA and the high speed data reading and writing between FPGA and DDR3 The bandwidth of the whole system i...

Страница 7: ...diagram you can see the interfaces and functions that the AV6150 FPGA Development Board contains 4 channel video input Select Techwell TW2867 can input 4 composite video signals PAL NTSC SECAM automat...

Страница 8: ...s The RTL8211EG chip supports 10 100 1000 Mbps network transmission rate 1 channel CMOS Input CMOS camera interface can be connected to ALINX s 300 000 pixel OV7670 camera module or 5 megapixel OV5640...

Страница 9: ...camera through the display VGA DVI HDMI interface which can realize 1080p for split screen display Our development board is equivalent to the digital video host in the Figure below Figure 2 1 1 Split...

Страница 10: ...Contact Email rachel zhou alinx com cn Figure 2 1 2 Set top box 3 Camera Module CMOS camera interface plug in ALINX 30 megapixel camera module or 5 megapixel camera module real time display 1080P vid...

Страница 11: ...monitors or TV to display HDMI video signals The video display for VGA and HDMI output is up to 1080P 60Hz Current computer monitors basically support one of VGA or HDMI inputs As long as one of the V...

Страница 12: ...FPGA Video Processing Development Platform AV6150 User Manual 12 55 Contact Email rachel zhou alinx com cn Part 3 AC6150 core board...

Страница 13: ...and DDR3 is up to 10Gb this configuration can meet the needs of 4 channels of 1080p video processing This core board also extends 168 IO ports 84 pairs of LVDS differential pairs which is a good choi...

Страница 14: ...s follows Name Specific parameters Logic Cells 147 443 Slices 23038 CLB flip flops 184 304 Block RAM kb 4 824 DSP Slices 180 Memory Controller Blocks 4 Chip Package BGA484 Spacing 1 0mm Speed Grade 2...

Страница 15: ...and core JTAG ports with DuPont cable To achieve core board program download and debug of the FPGA chip without the carrier board The following Figure 3 2 3 shows the JTAG interface on the core board...

Страница 16: ...e normal operation of DDR3 requires DDR3 address line and control line to provide termination voltage VTT and DDR3 chip reference voltage VREF VTT and VREF voltage are both 0 75V the following Figure...

Страница 17: ...DDR3_nCAS K4 DDR3_A 8 E3 DDR3_CKE D2 DDR3_A 9 E1 DDR3_CLK_P H4 DDR3_A 10 G4 DDR3_CLK_N H3 DDR3_nRAS K5 DDR3_DQ 8 P2 DDR3_nWE F2 DDR3_DQ 9 P1 DDR3_ODT J6 DDR3_DQ 10 R3 DDR3_RESET C3 DDR3_DQ 11 R1 DDR3...

Страница 18: ...system to store the boot image of the system These images mainly include FPGA bit files core application code and other user data files The specific models and related parameters of SPI FLASH are show...

Страница 19: ...Pin SPI_CLK Y21 SPI_CSn T5 SPI_DIN AB20 SPI_DOUT AA20 Part 3 5 Crystal oscillator on Core Board The core board carries a 50M active crystal oscillator and a 27M active crystal oscillator The 50MHz cl...

Страница 20: ...AB13 27MHz B10 Part 3 6 LED Light on Core Board There are 6 red LED lights on the AC6045 FPGA core board one of which is the power indicator light PWR one is the configuration LED light DONE and four...

Страница 21: ...alinx com cn Figure 3 6 2 Power Indicator and Configure Indicator on the Core Board The schematic diagram of the four user LED sections is shown below In Figure 3 6 3 When the FPGA pin output is logic...

Страница 22: ...repeated here The VCCO of the FPGA is separated from the VCCAUX power supply The purpose is to enable the BANK IO voltage of the FPGA to be flexibly adjusted Different output voltages are obtained by...

Страница 23: ...FPGA Video Processing Development Platform AV6150 User Manual 23 55 Contact Email rachel zhou alinx com cn Figure 3 7 1 Power Supply on core board schematic...

Страница 24: ...ormally the FPGA expansion baord needs to provide a 5V power supply to the core board through the expansion ports The power supply voltage of the core board ranges from 4 5V to 5 5V and the current is...

Страница 25: ...carrier board Otherwise current conflict may occur and the USB interface of the computer may be burned out Figure 3 8 2 Mini USB on the Core Board Part 3 9 Expansion Ports The core board has a total o...

Страница 26: ...FPGA Video Processing Development Platform AV6150 User Manual 26 55 Contact Email rachel zhou alinx com cn Figure 3 9 1 Expansion Ports P1...

Страница 27: ...FPGA Video Processing Development Platform AV6150 User Manual 27 55 Contact Email rachel zhou alinx com cn Figure 3 9 2 Expansion Ports P2...

Страница 28: ...FPGA Video Processing Development Platform AV6150 User Manual 28 55 Contact Email rachel zhou alinx com cn Figure 3 9 3 Expansion Ports P1 P2 on the Core Board...

Страница 29: ...ocessing Development Platform AV6150 User Manual 29 55 Contact Email rachel zhou alinx com cn Part 3 10 Structure Diagram Figure 3 10 1 AC6150 FPGA Core board Top view Figure 3 10 2 AC6150 FPGA Core b...

Страница 30: ...ough the previous function introduction you can understand the function of the carrier board part 4 channel Video Input TW2867 1 channel HDMI Input SiI9013 1 channel VGA Output ADV7123 1 channel HDMI...

Страница 31: ...screen display through VGA interface 2 After 4 channels of video signals are collected by TW2867 they are displayed on 4 split screen display through HDMI interface 3 Picture in picture PIP mode via...

Страница 32: ...put by the FPGA is 24 bit color of which 8 colors are red green and blue In the schematic design the 8 bit data of the red green and blue output of the FPGA is connected to the 3 way DA of the ADV7123...

Страница 33: ...HS F18 VGA_VS J17 VGA_R7 T22 VGA_R6 R22 VGA_R5 T21 VGA_R4 R20 VGA_R3 AB7 VGA_R2 AB8 VGA_R1 Y7 VGA_R0 AA8 VGA_G7 M22 VGA_G6 L22 VGA_G5 M21 VGA_G4 L20 VGA_G3 P22 VGA_G2 N22 VGA_G1 P21 VGA_G0 N20 VGA_B7...

Страница 34: ...hich supports up to 1080P 60Hz output and supports 3D output Among them IIC interface of SIL9134 is connected with STM32F103 SIL9134 is initialized and controlled by STM32F103 and other pins of SIL913...

Страница 35: ...18 9134_D 1 U13 9134_D 2 W18 9134_D 3 U14 9134_D 4 AB18 9134_D 5 AA18 9134_D 6 AB17 9134_D 7 AB14 9134_D 8 Y17 9134_D 9 AA14 9134_D 10 W13 9134_D 11 Y19 9134_D 12 T19 9134_D 13 AB19 9134_D 14 T20 9134...

Страница 36: ...up to 1080P 60Hz input and Support data output in different formats Among them IIC interface of SIL9013 is connected with STM32F103 SIL9013 is initialized and controlled by STM32F103 and other pins o...

Страница 37: ...3_D 0 W10 9013_D 1 W9 9013_D 2 Y10 9013_D 3 R8 9013_D 4 Y9 9013_D 5 R9 9013_D 6 V11 9013_D 7 AB9 9013_D 8 W11 9013_D 9 AA10 9013_D 10 AB12 9013_D 11 AB10 9013_D 12 Y15 9013_D 13 W12 9013_D 14 AB15 901...

Страница 38: ...SC SECAM automatic identification output BT656 multiplexable bus FPGA side demultiplexing save IO Among them the IIC interface and reset pin of TW2867 are connected to STM32F103 and the TW2867 is init...

Страница 39: ...rier board Video Input Interface Pin Assignment Pin Name FPGA Pin 2867_CLKP C11 2867_CLKN A11 2867_D 0 A3 2867_D 1 C5 2867_D 2 A4 2867_D 3 A5 2867_D 4 D6 2867_D 5 B6 2867_D 6 C6 2867_D 7 A6 Part 4 6 G...

Страница 40: ...1 8V voltage selection 3 3V AN 1 0 Auto negotiation configuration 10 100 1000M adaptive RX Delay RX clock 2ns delay Delay TX Delay TX clock 2ns delay Delay Mode RGMII or GMII selection RGMII Table 4 6...

Страница 41: ...o Processing Development Platform AV6150 User Manual 41 55 Contact Email rachel zhou alinx com cn Figure 4 6 1 Gigabit Ethernet Interface Schematic Figure 4 6 2 Gigabit Ethernet interface on the Carri...

Страница 42: ...2 MII Transmit Clock E_RXC H21 RGMII Receive Clock E_RXDV K21 Receive data valid signal E_RXD0 J20 Receive Data Bit0 E_RXD1 L19 Receive Data Bit1 E_RXD2 H22 Receive Data Bit2 E_RXD3 M20 Receive Data B...

Страница 43: ...FPGA Video Processing Development Platform AV6150 User Manual 43 55 Contact Email rachel zhou alinx com cn Figure 4 7 1 ARM STM32F103 Schematic Figure 4 7 2 STM32F103 on the FPGA carrier board...

Страница 44: ...150 User Manual 44 55 Contact Email rachel zhou alinx com cn At the same time the ARM chip also brings out real time clock EEPROM 4 LEDs and serial ports Part 4 7 1 Real Time Clock Figure 4 7 3 RTC Sc...

Страница 45: ...Contact Email rachel zhou alinx com cn ARM corresponding pin Pin Name ARM Pin RTC_SCLK 15 RTC_IO 16 RTC_RESET 14 Part 4 7 2 EEPROM Figure 4 7 5 EEPROM Schematic Figure 4 7 6 EEPROM on the carrier boar...

Страница 46: ...ment Platform AV6150 User Manual 46 55 Contact Email rachel zhou alinx com cn Part 4 7 3 LED Figure 4 7 7 LED Schematic Figure 4 7 8 LED on the carrier board ARM corresponding pin Pin Name ARM Pin LED...

Страница 47: ...ser Manual 47 55 Contact Email rachel zhou alinx com cn Part 4 7 4 USB to Serial Port Figure 4 7 9 USB to Serial Port Schematic Figure 4 7 10 USB to Serial Port on the expansion port ARM corresponding...

Страница 48: ...linx com cn Part 4 7 5 SD Card Slot ARM communicates with the Micro SD card through the SPI interface for reading and storing SD card data Figure 4 7 11 Mini SD Schematic Figure 4 7 12 SD Card Slot on...

Страница 49: ...After acquisition the monitor can be connected via HDMI or VGA interface for display OV7670 30W pixels output resolution is 640 480 OV5640 500W pixels output resolution up to 2592 1944 Regarding the...

Страница 50: ...nsion header J13 which is used to connect the ALINX modules or the external circuit designed by the user The expansion port has 40 signals of which 1 channel 5V power supply 2 channel 3 3 V power supp...

Страница 51: ...ct Email rachel zhou alinx com cn Figure 4 9 1 Expansion header J13 schematic Figure 4 9 2 Expansion header J13 on the Carrier board J13 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number...

Страница 52: ...18 34 A18 35 E16 36 C19 37 GND 38 GND 39 D3V3 40 D3V3 Part 4 10 JTAG Interface A JTAG interface is reserved on the FPGA carrier boardfor downloading FPGA programs or firmware to FLASH In order to prev...

Страница 53: ...plugged and unplugged Part 4 11 Buttons The FPGA carrier board contains two user buttons KEY1 KEY2 All buttons are connected to the normal IO of the FPGA The button is active low When the button is p...

Страница 54: ...GA PIN KEY1 J22 KEY2 K22 Part 4 12 Power Supply The power input voltage of the FPGA development board is DC5V It is converted into D3V3 D1V2 D1V8 three way power supply through three way DC DC power c...

Страница 55: ...Processing Development Platform AV6150 User Manual 55 55 Contact Email rachel zhou alinx com cn Figure 4 12 1 Power Design Schematic on the carrier board Figure 4 12 2 Power Supply circuit on the car...

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