Alinx AC7Z100 Скачать руководство пользователя страница 31

 

 

 

 

ZYNQ FPGA Development Board AC7Z100 User Manual 

 

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Amazon Store: https://www.amazon.com/alinx 

 

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SYS_RESET 

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GND 

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GND 

 

Pin assignment of J32 connector 

J32 Pin 

Signal Name 

ZYNQ Pin 

Number 

J32 Pin 

Signal Name 

ZYNQ Pin 

Number 

PS_MIO5 

C24 

PS_MIO17 

K21 

PS_MIO4 

E23 

PS_MIO18 

K20 

GND 

GND 

PS_MIO14 

B22 

PS_MIO19 

J20 

PS_MIO15 

C22 

10 

PS_MIO20 

M20 

11 

GND 

12 

GND 

13 

PS_MIO52 

D19 

14 

PS_MIO16 

L19 

15 

PS_MIO53 

C18 

16 

PS_MIO21 

J19 

17 

GND 

18 

GND 

19 

PS_MIO7 

B24 

20 

PS_MIO26 

M17 

21 

 

 

22 

PS_MIO25 

G19 

23 

GND 

24 

GND 

25 

PS_MIO40 

B20 

26 

PS_MIO24 

M19 

Содержание AC7Z100

Страница 1: ...ZYNQ7000 FPGA Development Board AC7Z100 System on Module...

Страница 2: ...ZYNQ FPGA Development Board AC7Z100 User Manual 2 33 Amazon Store https www amazon com alinx Version Record Version Date Release By Description Rev 1 0 2020 06 28 Rachel Zhou First Release...

Страница 3: ...cord 2 Part 1 AC7Z100 Core Board Introduction 4 Part 2 ZYNQ Chip 5 Part 3 DDR3 DRAM 8 Part 4 QSPI Flash 14 Part 5 eMMC Flash 16 Part 6 Clock Configuration 17 Part 7 LED Light 20 Part 8 Reset circuit 2...

Страница 4: ...L side can run at speeds up to 800MHz data rate 1600Mbps In addition two 256MBit QSPI FLASH and 8GB eMMC FLASH chips are integrated on the core board to boot the storage configuration and system files...

Страница 5: ...AC7Z100 User Manual 5 33 Amazon Store https www amazon com alinx Figure 1 1 AC7Z100 Core Board Front View Figure 1 2 AC7Z100 Core Board Rear View Part 2 ZYNQ Chip The FPGA core board AC7Z100 uses Xil...

Страница 6: ...rface GPIO etc The PS can operate independently and start up at power on or reset Figure 2 1 detailed the Overall Block Diagram of the ZYNQ7000 Chip Figure 2 1 Overall Block Diagram of the ZYNQ7000 Ch...

Страница 7: ...rfaces High bandwidth connection within PS and PS to PL The main parameters of the PL logic part are as follows Logic Cells 444K Look up tables LUTs 277440 Flip flops 554 800 18x25MACCs 2020 Block RAM...

Страница 8: ...The Specific Chip Model Definition of ZYNQ7000 Series Figure 2 3 The XC7Z100 chip used on the Core Board Part 3 DDR3 DRAM The FPGA core board AC7Z100 is equipped with four Micron 512MB DDR3 chips mod...

Страница 9: ...rate 1600Mbps and two DDR3 memory systems are connected to the BANK33 and BANK34 interfaces of the FPGA The specific configuration of DDR3 SDRAM is shown in Table 3 1 Bit Number Chip Model Capacity Fa...

Страница 10: ...B26 PS_DDR3_DQS1_P PS_DDR_DQS_P1_502 C29 PS_DDR3_DQS1_N PS_DDR_DQS_N1_502 B29 PS_DDR3_DQS2_P PS_DDR_DQS_P2_502 G29 PS_DDR3_DQS2_N PS_DDR_DQS_N2_502 F29 PS_DDR3_DQS3_P PS_DDR_DQS_P3_502 L28 PS_DDR3_DQ...

Страница 11: ...DQ20_502 E30 PS_DDR3_D21 PS_DDR_DQ21_502 F28 PS_DDR3_D22 PS_DDR_DQ22_502 G30 PS_DDR3_D23 PS_DDR_DQ23_502 F30 PS_DDR3_D24 PS_DDR_DQ24_502 J29 PS_DDR3_D25 PS_DDR_DQ25_502 K27 PS_DDR3_D26 PS_DDR_DQ26_502...

Страница 12: ...PS_DDR_CS_B_502 N22 PS_DDR3_RAS PS_DDR_RAS_B_502 N24 PS_DDR3_CAS PS_DDR_CAS_B_502 M24 PS_DDR3_WE PS_DDR_WE_B_502 N23 PS_DDR3_ODT PS_DDR_ODT_502 L23 PS_DDR3_RESET PS_DDR_DRST_B_502 F25 PS_DDR3_CLK0_P P...

Страница 13: ..._DDR3_D13 IO_L8P_T1_33 G4 PL_DDR3_D14 IO_L11P_T1_SRCC_33 G6 PL_DDR3_D15 IO_L10P_T1_33 H3 PL_DDR3_D16 IO_L18P_T2_33 E1 PL_DDR3_D17 IO_L14P_T2_SRCC_33 E3 PL_DDR3_D18 IO_L14N_T2_SRCC_33 D3 PL_DDR3_D19 IO...

Страница 14: ...10 IO_L24N_T3_34 G7 PL_DDR3_A11 IO_L11P_T1_SRCC_34 J9 PL_DDR3_A12 IO_L23N_T3_34 H9 PL_DDR3_A13 IO_L16P_T2_34 J11 PL_DDR3_A14 IO_L12P_T1_MRCC_34 K10 PL_DDR3_BA0 IO_L18P_T2_34 K11 PL_DDR3_BA1 IO_L19N_T3...

Страница 15: ...specific models and related parameters of QSPI FLASH are shown in Table 4 1 Position Model Capacity Factory U13 U14 W25Q256FVEI 256M bit Winbond Table 4 1 QSPI FLASH Specification QSPI FLASH is conne...

Страница 16: ...HS MMC interface with level support of 1 8V or 3 3V The data width of the eMMC FLASH and ZYNQ connections is 4 bits Due to the large capacity and non volatile nature of eMMC FLASH it can be used as a...

Страница 17: ...Name ZYNQ Pin Name ZYNQ Pin Number MMC_CCLK PS_MIO48_501 C19 MMC_CMD PS_MIO47_501 A18 MMC_D0 PS_MIO46_501 F20 MMC_D1 PS_MIO49_501 D18 MMC_D2 PS_MIO50_501 A19 MMC_D3 PS_MIO51_501 F19 Part 6 Clock Conf...

Страница 18: ...FPGA core board AC7Z100 The input of the clock is connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip The schematic diagram is shown in Figure 6 2 Figure 6 2 Active crystal oscillat...

Страница 19: ...GA BANK34 which can be used to drive the DDR3 controller and user logic in the FPGA The schematic diagram of the clock source is shown in Figure 6 3 Figure 6 3 PL system clock source PL Clock pin assi...

Страница 20: ...al Name ZYNQ Pin BANK111_CLK1_P AC8 BANK111_CLK1_N AC7 Part 7 LED Light There are 2 red LED lights on the AC7Z100 FPGA core board one of which is the power indicator light PWR one is the configuration...

Страница 21: ...reset input signal is connected to the reset button on the carrier board The reset output is connected to the PS reset pin of the ZYNQ chip The user can use the buttons on the carrier board to reset...

Страница 22: ...er board The power supply design diagram on the FPGA board is shown in Figure 9 1 Figure 9 1 Power interface section in the schematic 5V generates 1 0V ZYNQ core power through DCDC power chip EM2130L0...

Страница 23: ...wer Supply Function 1 0V ZYNQ PS and PL section Core Voltage 1 8V ZYNQ PS and PL partial auxiliary voltage BANK501 BANK35 eMMC 3 3V ZYNQ Bank0 Bank500 Bank9 Bank12 Bank13 QSIP FLASH Clock Crystal 1 5V...

Страница 24: ...pment Board AC7Z100 User Manual 24 33 Amazon Store https www amazon com alinx Figure 9 2 Power Supply on the AX7Z100 Core Board Part 10 AC7Z100 Core Board Size Dimension Figure 10 1 AC7Z100 Core Board...

Страница 25: ...signal J31 connects JTAG and BANK35 IO 1 8V level standard J32 connects PS MIO IO and 5V power supplies of the BANK11 BANK12 Pin assignment of J29 connector J29 Pin Signal Name ZYNQ Pin Number J29 Pi...

Страница 26: ...GND 55 B10_L2_P AH18 56 B10_L15_P AF18 57 B10_L2_N AJ18 58 B10_L15_N AF17 59 GND 60 GND 61 B10_L4_P AJ16 62 B10_L6_P AH17 63 B10_L4_N AK16 64 B10_L6_N AH16 65 GND 66 GND 67 B10_L16_P AE16 68 B10_L24_N...

Страница 27: ...3 118 B10_L21_P AB12 119 GND 120 GND Pin assignment of J30 connector J30 Pin Signal Name ZYNQ Pin Number J30 Pin Signal Name ZYNQ Pin Number 1 BANK111_TX0_N AB1 2 BANK111_RX0_N AC3 3 BANK111_TX0_P AB2...

Страница 28: ...5 BANK112_CLK0_N N7 56 BANK112_CLK1_N R7 57 BANK112_CLK0_P N8 58 BANK112_CLK1_P R8 59 GND 60 GND 61 BANK109_RX2_N AG7 62 BANK110_RX0_N AH5 63 BANK109_RX2_P AG8 64 BANK110_RX0_P AH6 65 GND 66 GND 67 BA...

Страница 29: ...109_CLK0_P AD10 112 BANK110_CLK0_P AA8 113 GND 114 GND 115 116 117 118 119 GND AA12 120 GND AA12 Pin assignment of J31 connector J31 Pin Signal Name ZYNQ Pin Number J31 Pin Signal Name ZYNQ Pin Number...

Страница 30: ...45 B35_L4_P J14 46 B35_L23_N A14 47 GND 48 GND 49 B35_L1_N L14 50 B35_L21_P B15 51 B35_L1_P L15 52 B35_L21_N A15 53 GND 54 GND 55 B35_L16_N C16 56 B35_L14_P D15 57 B35_L16_P D16 58 B35_L14_N D14 59 G...

Страница 31: ...GND 120 GND Pin assignment of J32 connector J32 Pin Signal Name ZYNQ Pin Number J32 Pin Signal Name ZYNQ Pin Number 1 PS_MIO5 C24 2 PS_MIO17 K21 3 PS_MIO4 E23 4 PS_MIO18 K20 5 GND 6 GND 7 PS_MIO14 B2...

Страница 32: ...D 49 B12_L4_N AA29 50 PS_MIO32 K17 51 B12_L4_P Y28 52 PS_MIO33 G22 53 GND 54 GND 55 B12_L19_P AH28 56 PS_MIO34 K18 57 B12_L19_N AH29 58 PS_MIO35 G21 59 GND 60 GND 61 B12_L3_P Y26 62 PS_MIO28 L17 63 B1...

Страница 33: ...L9_P AF23 93 B11_L21_P Y22 94 B11_L9_N AF24 95 GND 96 GND 97 B11_L22_N AB24 98 B11_L10_N AE21 99 B11_L22_P AA24 100 B11_L10_P AD21 101 GND 102 GND 103 B11_L7_P AC24 104 B11_L24_P AC22 105 B11_L7_N AD2...

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