2 ) V - V C O C i r c u i t
S W Q 7 0 4 i s t u r n e d O N , a n d t h e d e s i r e d f r e q u e n c y i s o s c i l l a t e d d i r e c t l y i n C o l p i t t s
o s c i l l a t i n g c i r c u i t c o n s i s t i n g o f F E T Q 7 5 7 .
V C O c o n t r o l v o l t a g e i s a d d e d t o t h e
v a r i c a p s D 7 0 2 a n d D 7 0 3 , a n d t h e o s c i l l a t i n g f r e q u e n c y i s t u n e d .
S W 2 b e c o m e s " H " w h i l e r e c e i v i n g , a n d Q 7 0 1 a n d D 7 0 1 a r e t u r n e d O N t o s h i f t t h e
o s c i l l a t i n g f r e q u e n c y .
3) V Sub U-VCO Circuit
S W Q 7 5 5 i s t u r n e d O N , a n d t h e d e s i r e d f r e q u e n c y i s o s c i l l a t e d d i r e c t l y i n C o l p i t t s
o s c i l l a t i n g c i r c u i t c o n s i s t i n g o f F E T 7 5 7 .
V C O c o n t r o l v o l t a g e i s a d d e d t o t h e
v a r i c a p s D 7 5 1 a n d D 7 5 2 , a n d t h e o s c i l l a t i n g f r e q u e n c y i s t u n e d .
( Q 7 0 4 i s t u r n e d O F F i n 1 4 4 M H z b a n d , a n d t h e o s c i l l a t i o n i s s t o p p e d . )
4) U-VCO Circuit
S W Q 8 0 4 i s t u r n e d O N , a n d t h e d e s i r e d f r e q u e n c y i s o s c i l l a t e d d i r e c t l y i n C o l p i t t s
o s c i l l a t i n g c i r c u i t c o n s i s t i n g o f F E T Q 8 0 2 .
V C O c o n t r o l v o l t a g e I s a d d e d t o t h e
v a r i c a p s D 8 0 2 a n d D 8 0 3 , a n d t h e o s c i l l a t i n g f r e q u e n c y i s t u n e d .
S W 2 b e c o m e s " L " w h i l e r e c e i v i n g , a n d Q 8 0 1 a n d D 8 0 1 a r e t u r n e d O F F t o s w i t c h
t h e o s c i l l a t i n g f r e q u e n c y .
5) U Sub V-VCO Circuit
S W Q 8 5 5 i s t u r n e d O N , a n d t h e d e s i r e d f r e q u e n c y i s o s c i l l a t e d d i r e c t l y i n C o l p i t t s
o s c i i i a t i n g c i r c u i t c o n s i s t i n g o f F E T Q 8 5 7 .
V C O c o n t r o l v o l t a g e i s a d d e d t o t h e
v a r i c a p s D 8 5 1 a n d D 8 5 2 , a n d t h e o s c i l l a t i n g f r e q u e n c y i s t u n e d .
( Q 8 0 4 i s t u r n e d O F F i n 4 3 0 M H z b a n d , a n d t h e o s c i l l a t i o n i s s t o p p e d . )
6) Shift SW (SW1) Circuit
W h e n P T T i s t u r n e d O N , S W 1 o f P L L I C b e c o m e s " H " m o m e n t a r i l y , a n d t h e s w i t c h
Q 7 5 9 ( V H F ) o r Q 8 5 9 ( U H F ) i s t u r n e d O N .
T h e c o n s t a n t o f L P F i s c h a n g e d a n d t h e l o c k u p t i m e f r o m r e c e i v i n g t o t r a n s m i t t i n g
i s s h o r t e n .
4. Front CPU and Peripheral Circuit
1) Reset Circuit
W h e n B p o w e r s u p p l y i s t u r n e d O N , " L " p u l s e o f a b o u t 4 0 m s i s o u t p u t f r o m I C 5 0 3
w i t h R e s e t F u n c t i o n P i n 4 , a n d C P U I C 5 0 1 i s r e s e t .
W h e n B p o w e r s u p p l y i s t u r n e d O F F , t h e d e c r e a s i n g o f 5 V l i n e i s d e t e c t e d i n
I C 5 0 3 . T h e o u t p u t i s s h i f t e d f r o m " H " t o " L "
l e v e l .
2) Microphone Key Input Circuit
W h e n t h e s w i t c h ( P T T , U P o r D O W N ) o n t h e m i c r o p h o n e i s t u r n e d O N , " L " l e v e l i s
i n p u t t o C P U I C 5 0 1 s i m u l t a n e o u s l y .
3) LCD Display Circuit
L C D d i s p l a y c i r c u i t c o n s i s t s o f L C D d r i v e r I C 5 0 2 , i t s p e r i p h e r a l c i r c u i t a n d L C D .
T h e l i g h t i n g m o d e i s d y n a m i c l i g h t i n g o f 1 / 3 d u t y a n d 1 / 3 b i a s , a n d t h e s e r i a l d a t a
o f t h e c o n t e n t i s t r a n s m i t t e d t o t h e L C D d r i v e r f r o m V 1 ~ V 5 o f I C 5 0 1 .
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Содержание DR-610E
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