Alinco DR-235 TMk III, Руководство по обслуживанию, Страница: 5 / 40

3) PLL Synthesizer Circuit DR- 235
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in IC116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6.25 kHz.
2. Reference Frequency
Circuit
e re^erence frequency appropriate for the channel steps is obtained by
dividing the 12.8 MHz reference oscillation (X102) by 4250 or 3400,
according to the data from the CPU (IC1). When the resulting frequency is
5 kHz, channel steps of 5, 10,15, 20, 25, 30, and 50 kHz are used. When
it is 6.25 kHz, the 12.5 kHz channel step is used.
3. Phase Comparator Circuit
The PLL (IC116) uses the reference frequency, 5 or 6.25kHz. The phase
comparator in the IC116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25kHz, which is
obtained by the internal divider in IC116.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the
reference frequency and VCO output frequency, the charge pump output
(pin 5) of IC116 generates a pulse signal, which is converted to DC
voltage by the PLL loop filter and input to the varicap of the VCO unit for
oscillation frequency control.
5. VCO Circuit
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determined in the CPU (IC1) and
PLL circuit is input to the varicaps (D122 and D123). This change the
oscillation frequency, which is amplified by the VCO buffer (Q134) and
output from the VCO area.
4 ) C P U a n d P e r i p h e r a l C i r c u i t s
1. LCD Display Circuit
2. Dimmer Circuit
3. Reset and Backup
The CPU turns ON the LCD via segment and common terminals with 1/4
the duty and 1/3 the bias, at the frame frequency is 64Hz.
The dimmer circuit makes the output of pin 13 of CPU (IC1) into "H" level
at set mode, so that Q9 and Q3 will turn ON to make the lamp control
resistor R84 short and make its illumination bright. But on the other hand,
if the dimmer circuit makes pin 13 into "L" level, Q9 and Q3 will turn OFF,
R84's illumination will become dimmer as its hang on voltage falls down in
the working LED (D11, D2, D5, D3 and D6).
When the power form the DC cable increases from Circuits 0 V to 2.5 or
more, "H" level reset signal is output form the reset IC (IC4) to pin 33 of
the CPU (IC1), causing the CPU to reset. The reset signal, however, waits
at 100, and does not enter the CPU until the CPU clock (X1) has
stabilized.