[AKD4133-A]
< KM119500>
2016/11
[3] DIP switches settings
(3-1). Setting for SW200 / SW300
(Sets AK4118A (U200 / U300) audio format and master clock setting)
No.
Switch Name
Function
default
1
DIF2
Set-up of DIF2 pin.
H
2
DIF1
Set-up of DIF1 pin.
L
3
DIF0
Set-up of DIF0 pin.
H
4
OCKS1
Set-up of OCKS1 pin.
L
5
OCKS0
Set-up of OCKS0 pin.
L
Table 3-1. SW200 / SW300 Setting
Mode
DIF2 pin
DIF1 pin
DIF0 pin
DAUX
SDTO
LRCK
BICK
I/O
I/O
0
0
0
0
24bit, Left
justified
16bit, Right
justified
H/L
O
64fs
O
1
0
0
1
24bit, Left
justified
18bit, Right
justified
H/L
O
64fs
O
2
0
1
0
24bit, Left
justified
20bit, Right
justified
H/L
O
64fs
O
3
0
1
1
24bit, Left
justified
24bit, Right
justified
H/L
O
64fs
O
4
1
0
0
24bit, Left
justified
24bit, Left
justified
H/L
O
64fs
O
5
1
0
1
24bit, I
2
S
24bit, I
2
S
L/H
O
64fs
O
default
6
1
1
0
24bit, Left
justified
24bit, Left
justified
H/L
I
64-128fs
I
7
1
1
1
24bit, I
2
S
24bit, I
2
S
L/H
I
64-128fs
I
Table 3-2. Audio format (AK4118A)
OCKS1 pin
OCKS0 pin
(X
’
tal)
MCKO1
MCKO2
fs (max)
0
0
256fs
256fs
256fs
96 kHz
default
0
1
256fs
256fs
128fs
96 kHz
1
0
512fs
512fs
256fs
48 kHz
1
1
128fs
128fs
64fs
192 kHz
Table 3-3. Master Clock Frequency Select (AK4118A)
(3-2). Setting for SW500 (AK4133 (U100) )
No.
Switch Name
Function
default
1
SD
Digital Filter select setting.
L
2
CM0
Clock select or Mode setting 0.
H
3
CM1
Clock select or Mode setting 1.
L
4
TEST
TEST pin setting.
L
5
SEL33
No use.
L
6
VSEL
Digital Power select
L : DV18 is Output
H : DV18 is Power supply
L
7
ODIF
Audio Interface Format for Output PORT.
H
8
IDIF
Digital Input Format setting.
H
Table 3-4. SW500 Setting (AK4133)
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