ASAHI KASEI
[AKD4127-A]
<KM085601>
2006/11
- 3 -
(2) All clocks are fed through the 10pin port
When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
JP2
IBICK
JP3
SDTI
JP4
ILRCK
•
SW3 setting (See Table 2)
Upper-side is “H” and lower-side is “L”.
SW3 No.
Name
ON (“H”)
OFF (“L”)
Default
1 DITH Dither
ON Dither
OFF L
2 PLL2
H
3 PLL1
L
4 PLL0
PLL Mode Setting
Refer to Table 3
H
5 IDIF0
L
6 IDIF1
H
7 IDIF2
AK4127 Audio I/F Format Setting
Refer to Table 4
L
Table 2. SW3 Setting
Mode Master
/
Slave PLL2 PLL1 PLL0
ILRCK
Freq IBICK
Freq IMCLK
SMUTE
(Note 4)
0 L
L
L
8k
∼
96kHz
1 L
L
H
Manual
2 L
H
L
8k
∼
216kHz
16k
∼
216kHz
(Note 1)
Depending on
IDIF2-0
Not
needed.
Semi-Auto
3 L
H
H Reserved
4 H
L
L
32fsi
(Note
3)
5 H
L
H 64fsi
6 H
H
L 128fsi
Manual
7
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
H H H
8k
∼
216kHz
(Note 2)
64fsi
Not
needed.
Semi-Auto
8 L
L
L
8k
∼
216kHz
128fs
9 L
L
H
8k
∼
108kHz
256fs
10 L
H
L
8k
∼
54kHz
512fs
Manual
11 L
H
H
8k
∼
216kHz
128fs Semi-Auto
12 H
L
L
8k
∼
216kHz
192fs
13 H
L
H
8k
∼
108kHz
384fs
14 H
H
L
8k
∼
54kHz
768fs
Manual
15
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
H H H
8k
∼
216kHz
64fs
192fs Semi-Auto
Table 3. PLL Setting (Input PORT)
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter” in the
datasheet.
470
Ω
, 0.22
µ
F and 1nF are implemented on the evaluation board.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I
2
S Compatible.
Note 4. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode in the datasheet.
