Akai PDP42Z5TA - 42" Plasma TV, Руководство по обслуживанию

Страница: 85 / 141

CE2836
CREGB, ADC Input Enable (
ADRS
=hex0B, default=hex01)
AMUX[4:0]: ADC Input Channel Enable.
00001: - AIN1
00010: - AIN2
00100: - AIN3
01000: - AIN4
10000: - AIN5
CREGC, ADC Input Gain Selection (
ADRS
=hex0C, default=hex99)
LGAIN[3:0] is for ADC Left Channel Gain Select While RGAIN[3:0] is for Right Channel Gain Select
1111 corresponds to +6 dB and 0000 to -9 dB with -1dB step
CREGD, Chip Soft Reset (
ADRS
=hex0D, default=hex92)
Chip Soft Reset; A write of all zeros to this register will reset the chip except the Command Registers.
Another write of hex92 is required to enable to chip again.
ADDR[3:0]
CREG1[7:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Hex 0B X X X AMUX[4:0]
Default Value 1 0 0 0 0 0 0 1
ADDR[3:0]
CREG1[7:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Hex 0C LGAIN[3:0] RGAIN[3:0]
Default Value 1 0 0 1 1 0 0 1
ADDR[3:0]
CREG1[7:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Hex 0D RESET[7:0]
Default Value 1 0 0 1 0 0 1 0
83／148