Akai DV-R3110SS, Руководство по обслуживанию

Страница: 37 / 47

69 70
U16 ZR36732PQC PINS DESCRIPTION U16 ZR36732PQC PINS DESCRIPTION - CONTINUED
Pin No. Pin Name Type Description
Reset,Standby and Idle Status Interface
124 RESET# I Reset input.Once de-asserted,the Decoder starts the initialization process.
122 STNDBY# I Stand-by input. When asserted together with RESET#, all outputs and bidirectional
pins float, such that the Decoder is electrically disconnected from its surroundings.
All internal clocks are disabled,and the power consumption is minimized.
160 IDLE 3-S Idle, Init and Reset states indication output.
Host Interface
2 HWID I Determines the width of the host interface data bus.It is allowed to be changed only
during RESET,A low level (GNDP) Configures the Decoder to an 8-bit host data
interface, a high level (VDDP) to 16-bit width.
1 HORD I Determines the order of bytes on the host interface data bus in case of 16-bit width
(HWID at VDDP). It is allowed to be changed only during RESET. A low level (GNDP)
configures the Decoder to input/output the m.s. Byte on HD [ 15:8 ]; A high level
(VDDP) to input/output the m.s.byte on HD [ 7:0 ], Must be at GNDP if the houst
data bus is 8 bits.
4 HTYPE I Determines the protocol type for the 8 and 16 bits modes host interface.It is allowed
to be changed only during RESET.A low level (GNDP) configures the Decoder to
type A, a high level (VDDP) to type B.
17,18 HD[7],HD[6] 3-S For 16 bits mode,the 8 I.S. Data lines of host data bus. For 8 bits mode,only these
20,21 HD[5],HD[4] signals are defined as host data signals.
22,23 HD[3],HD[2]
24,25 HD[1],HD[0]
9,11 HD[11],HD[10] 3-S When HWID is connected to VDDP,these are data lines 11:8 of the 16-bit host
13,15 HD[9],HD[8] data bus.
5,6 HD[15],HD[14] 3-S When HWID is connected to VDDP,these are data lines 15:12 of the 16-bit host
7,8 HD[13],HD[12]
data bus. When HWID is connected to GNDP, these are the CD-DSPI
2
S input port.
pins as explained in the CD-DSP pin description.
27,28 HA[3],HA[2] I Host address inputs,These input signals indicate the register accessed in every
29,30 HA[1],HA[0] cycle on the host interface.
32 HCS# I Host chip-select input.
31 HWR#-HR/W# I In host protocol Type A(HTYPE= GNDP):HR/W# This input determines the direction
of the host access.
In host protocol Type B (HTYPE=VDDP):HWR#.Host write input.
34 HRD#-HDS# I In host protocol Type A (HTYPE = GNDP): HDS#. Data strobe input (active low)
In host protocol Type B (HTYPE=VDDP):HRD#.Host read input.(active low.)
36 HRDY 3-S Host ready output. When this signal is tri-stated (i.e, is requires a pull-up resistor),
up to SysConfig.CodBurstLed bytes of code can be written to the Decoder with no
need to poll its condition in between. When HRDY is low during a host access,
the Decoder may still receive at least two additional bytes of code without corrupting
the data.
37 HIRQ# 3-S Interrupt request. This output signal requests an interrupt from the host controller,
if one of the events associated to interrupts occurs,and it is not masked-off. It is
de-asserted if the host responds to the interrupt by reading the interrupt status
register, or if the host disables the interrupt, or after RESET
Deassertion of the HIRQ# output has two modes: De-activated and then tri-stated
or directly to is a tri-state condition. The pin needs external pull-up resistor.
39 HACK# HACK# Host acknowledge output. In protocol A,the Decoder indicates that a read or write
cycle is completed by asserting this output.In protocol B,this signal is used by the
Decoder to indicate a wait state that may be used by fast hosts. In protocol B the
host may ignore the HACK# signal.
When this signal is deasserted it is de-activated and then tri-stated. This pin needs
an external pull-up resistor.
Pin No. Pin Name Type Description
General Purpose I/O (Host Interface)
134 GPAIO 3-S General purpose input/output pin,monitored/controlled by the audio processor
software.After RESET, this pin is defined as input.Its definition can be configured
through ADP commands.
145 GPSI I General purpose input,monitored by the system de-multiplexer/video processor
software.
143 GPSO O General purpose output,controlled by the system de-multiplexer/video processor
software. After RESET it outputs a low level.
DVD-DSP interface
151 DVDREQ O DVD-DSP data request output (programmable polarity)
149 DVDVALID I DVD-DSP data valid input (programmable polarity)
148 DVDSOS I DVD-DSP start of sector input (programmable polarity)
159,158 DVDAT[7],[6] I DVD-DSP data input bus.
157,156 DVDAT[5],[4]
155,154 DVDAT[3],[2]
153,152 DVDAT[1],[0]
150 DVDSTRB I DVD-DSP data bit strobe (clock)input. Programmable polarity.
147 DVDERR I DVD-DSP error indication input.Programmable polarity.
5 CDERR I When HWID is connected to GNDP, these are the CD DSPI
2
S input port pins as follows:
6 CDFRM CDERR: data error indication input
7 CDDAT CDFRM: Ieft/right channel frame input
8 CDCLK CDDAT: data input
CDCLK:bit clock input
When HWID is connected to VDDP, these are HD [15:12] of the host data bus ,as
explained in the host interface pin description.
Video Syncs and Clocks Interface
127 VCLKx2 3-S Main video clock.27.000MHz.
92 VCLK 3-S A division by two of the VCLKx2 signal. This signal is used as a sync qualifier.
95 HSYNC 3-S Horizontal sync. Polarity and duration are programmable.
93 VSYNC 3-S Vertical sync. Polarity and duration are programmable.
96 FI 3-S Field indication. Polarity is programmable.
Analog Video Encoder Interface
102 CVBS/G/Y O When the Decoder outputs composite video, this line is CVBS
(DAC A) When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV,this line is the Y output
105 Y/R/V O When the Decoder outputs the composite video,this line is Y
(DAC B) When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV,this line is the V output
106 C/B/U O When the Decoder outputs the composite video,this line is C
(DAC C) When the Decoder outputs RGB,this line is the Blue output
When the Decoder outputs YUV,this line is the U output
103 CVBS/C O When the Decoder outputs any of the types of video,this line can be programmed to
(DAC D) output either composite or C.
108 RSET I Resistive load for gain adjustment of the DACs
111 VREF I Voltage reference for gain adjustment of the DACs
100 COSYNC 3-S Composite sync output,Active only when RGB analog output is selected. Otherwise,
the signal is low.
Digital Audio Interface
131 AMCLK 3-S Audio Master Clock input/output.128,192,256 or 384 times the sampling frequency
(programmable)
133 S/PDIF O S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately
(AOUT[3]) can be used as a fourth audio output. After RESET this pin outputs low level.
138,137 AOUT[2],[1] O Serial outputs of digital stereo audio.
136 AOUT[0]