- 39 -
PIN No
PIN Name
I/O
1
VSSA
2
VSSD
3
N.C.
4
SCL
5
SDA
6
CS0
7
VCS
8
N.C.
9
DAVN
10
EHB
11
TI
12
PD1
13
N.C.
14
PD2/VCO2
15
VCO1
16
I
REF
17
CVBS
18
N.C.
19
VDDD
20
VDDA
Test input; activates test mode when pulled high.
Connect to ground for operating mode.
Connector of the loop filter for the SYSPLL.
Input to the voltage controlled oscillator #1 of the DAPLL
Not connected
Positive supply voltage for the digital ci5V nom
Positive supply voltage for the analog ci5V nom
Reference current input for the on-chip analog circuit.
Composite video signal input.
Serial Data Input of I
2
C Bus
Not connected
Data avilable output low, when VPS data is receiver.
Output signaling the presence of the first field active high
I.C PIN DESCRIPTIONS (VPS IC : SDA5650) : IC
82
Phase detector/charge pump output of data PLL
Not connected
Chip selet input determining the I
2
C Bus addresses;
20H/21H, when pulled low
23H/23H, when pulled high
Function
Analog Ground (0V)
Video Composite Sync output from Sync silcer used for PLL based
clock generate
Digital Ground (0V)
Not connected
Serial Clock Input of I
2
C Bus
P-DSO-20-1
PIN ASSIGNMENTS
BLOCK DIAGRAM
Содержание ADR-5800DI
Страница 7: ...MECHANISM DVD RW AV BOARD BOARD BOTTOM BOARD SMPS SCART BOARD PRINCIPAL PARTS LOCATION 7 ...
Страница 35: ... 35 BLOCK DIAGRAM PIN ASSIGNMENTS ...
Страница 48: ... 48 EXPLODED VIEW 2 ...
Страница 49: ...BLOCK DIAGRAM 49 ...
Страница 50: ...WIRING DIAGRAM 50 ...
Страница 51: ...FRONT BOARD SCHEMATIC DIAGRAMS 51 ...
Страница 52: ...BOTTOM BOARD 51 ...
Страница 56: ... 55 AV BOARD 1 ...
Страница 57: ... 56 AV BOARD 2 ...
Страница 58: ... 57 AV BOARD 3 ...
Страница 59: ... 58 AV BOARD 4 ...
Страница 61: ... 64 AV BOARD TOP VIEW AV BOARD BOTTOM VIEW ...
Страница 62: ...SMPS BOARD 65 ...