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– 44 –
Pin No.
Pin Name
I/O
Description
21
FDO
O
Focus control output terminal. D/A output.
22
SPDO
O
Spindle control output terminal. D/A output.
23
SLDO
O
Sled control ouput terminal. D/A output.
24
GPDAC
O
Servo D/A common output terminal. (Not used)
25
CONT4
I/O
Common input/output terminal 4. (Used as a CD driver mute pin)
26
CONT5
I/O
Common input/output terminal 5. (Not used)
27
SBCK/CONT6
I/O
Common input/output terminal 6, or sub code read clock input terminal.
(Used as a CD pickup inside limit switch)
28
SBCK/FG
I
Sub code read clock input terminal / FG signal input terminal / External emphasis setting
terminal. Terminal function is decided by command. (Connected to 0 V)
29
DEFECT
O
Defect terminal. (Not used)
30
V/P
O
Automatic switching monitor output terminal for rough servo/phase control.
"H"=Servo, "L"=Phase servo. (Not used)
31
FSEQ
O
Sync signal detection output terminal. "H"=Sync signal detected from EFM signal and internally
generated sync signal are agreed. (Not used)
32
MONI1
O
Internal signal monitor terminal 1.
33
MONI2
O
Internal signal monitor terminal 2.
34
MONI3
O
Internal signal monitor terminal 3.
35
MONI4
O
Internal signal monitor terminal 4.
36
MONI5
O
Internal signal monitor terminal 5.
37
VSS1
-
Digital grounding terminal. (Connected to 0 V)
38
VDD
-
Digital power supply terminal.
39
DOUT
O
Digital OUT output terminal. (EIAJ format) (Not used)
40
TEST
I
Test input terminal. (Connected to GND)
41
LVDD
-
L channel power supply terminal.
42
LCHO
O
L channel output terminal.
43
LVSS
-
L channel grounding terminal. (Connected to 0 V)
44
RVSS
-
R channel grounding terminal. (Connected to 0 V)
45
RCHO
O
R channel output terminal.
46
RVDD
-
R channel power supply terminal.
47
XVDD
-
Crystal oscillation power supply terminal.
48
XOUT
O
Connection terminal for 16.9344MHz crystal oscillation.
49
XIN
I
50
FSX/16MIN
I/O
7.35kHz sync signal output terminal. Or external clock input terminal for DF, DAC. (Not used)
51
XVSS
-
Grounding terminal for crystal oscillation. (Connected to 0 V)
52
C2F
O
C2 flag output terminal. (Not used)
53
EFLG
O
C1 and C2 correction monitor terminal. (Not used)
54
16MOUT
O
16.9344MHz output terminal. (Not used)
55
ASLRCK
I
L/R clock input terminal. (Connected to 0 V)
56
ASDACK
I
Bit clock input terminal. (Connected to 0 V)
57
ASDFIN
I
L/R channel data input terminal. (Connected to 0 V)
Содержание XR-EM50
Страница 31: ... 31 SCHEMATIC DIAGRAM 4 TUNER ...
Страница 38: ... 38 IC BLOCK DIAGRAM ...
Страница 39: ... 39 ...
Страница 40: ... 40 FL 11 BT 193GNK GRID ASSIGNMENT AND ANODE CONNECTION GRID ASSIGNMENT ANODE CONNECTION ...
Страница 46: ... 46 VOLTAGE CHART ...
Страница 47: ... 47 ...
Страница 48: ... 48 ...
Страница 50: ... DECK SECTION JW38 C651 Lch C652 Rch L451 DECK C B MOTOR TAPE MECHANISM R P HEAD MAIN C B CONDUCTORSIDE 50 ...
Страница 65: ... 65 CD MECHANISM EXPLODED VIEW 2 2 3ZG 2 A 3 6 2 5 1 9 10 4 7 8 ...
Страница 73: ...2 11 IKENOHATA 1 CHOME TAITO KU TOKYO 110 8710 JAPAN TEL 03 3827 3111 9301944 9430209 921338 ...