-78-
1
2-4
5-9
10
11
12-14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pin No.
Pin Name
I/O
Description
IC DESCRIPTION-9/10 (ADV7170K)-1/1
AVDD
P5-7
P8-12
GND
AVDD
P13-15
_____________
HSYNC
_____________
VSYNC
______________
BLANK
ALSB
GND
AVDD
GND
_____________
RESET
SCLOCK
SDATA
COMP
CHROMA
LUMI
AVDD
GND
AVDD
B/COMP/U
COMPOSITE
VREF
RSET
—
I
I
—
—
I
I
I
I
I
—
—
—
I
I
I/O
O
O
O
—
—
—
O
O
I/O
I
I
I
I
I
Power Supply. (3.3 V)
Pixel Port. (Digital video signal in)
Pixel Port. (Conneted to Ground.)
Ground Pin.
Power Supply. (3.3 V)
Pixel Port. (Conneted to Ground.)
_____________
HSYNC Control Signal.
_____________
VSYNC Control Signal.
Video Blanking Control Signal. (Pull down)
TTL Address Input. (Pull up)
Ground Pin.
Power Supply. (3.3 V)
Ground Pin.
The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default
mode.
MPU Port Serial Interface Clock Input
MPU Port Serial Data Input/Output
Compensation Pin. (Pull up)
RED/S-Video C/V Analog Output
GREEN/S-Video Y/Y Analog Output
Power Supply. (3.3 V)
Ground Pin.
Power Supply. (3.3 V)
BLUE/Composite/U Analog Output
PAL/NTSC Composite Video Output.
Voltage Reference Input for DACs or Voltage Reference Output. (Pull up)
A 150
Ω
resistor connected from this pin to GND is used to control full-scale amplitudes of the
video signals.
This pin is subcarrier reset.
Teletext Data Request Signal/Defaults to GND when Teletext not Selected. (Pull down)
Teletext Data/Defaults to VAA when Teletext not Selected. (Pull up)
Pixel Port. (Digital video signal in)
Ground Pin.
TTL Clock Input.Requires a stable 27 MHz reference Clock for standard operation.
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
