-60-
Pin No.
Pin Name
I/O
Description
XTL1
XRST
VDDS
D0
D1
D2
D3
D4
D5
D6
D7
VSS
A0
A1
A2
A3
A4
VDD
A5
A6
A7
A8
VSS
A9
A10
A11
A12
VDD
XINIT0
XINIT1
MDB0
MDB1
MDB2
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
203
204
205
206
207
208
I
I
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I
I
I
I
I
—
I
I
I
I
—
I
I
I
I
I
I
I
I
I
—
O
O
I/O
I/O
I/O
Terminal to connect external crystal oscillator between XTL1 and XTL2.
Chip reset negative logic input signal.
Standard 5.0 V digital power supply terminal.
8 bit data bus [0].
8 bit data bus [1].
8 bit data bus [2].
8 bit data bus [3].
8 bit data bus [4].
8 bit data bus [5].
8 bit data bus [6].
8 bit data bus [7].
Digital ground terminal.
Input signal [0] of address selection sub-CPU CXD1866 internal register.
Input signal [1] of address selection sub-CPU CXD1866 internal register.
Input signal [2] of address selection sub-CPU CXD1866 internal register.
Input signal [3] of address selection sub-CPU CXD1866 internal register.
Input signal [4] of address selection sub-CPU CXD1866 internal register.
Standard 3.3 V digital power supply terminal.
Input signal [5] of address selection sub-CPU CXD1866 internal register.
Input signal [6] of address selection sub-CPU CXD1866 internal register.
Input signal [7] of address selection sub-CPU CXD1866 internal register.
Input signal [8] of address selection sub-CPU CXD1866 internal register.
Digital ground terminal.
Input signal [9] of address selection sub-CPU CXD1866 internal register.
Input signal [10] of address selection sub-CPU CXD1866 internal register.
Input signal [11] of address selection sub-CPU CXD1866 internal register.
Input signal [12] of address selection sub-CPU CXD1866 internal register.
Input signal [13] of address selection sub-CPU CXD1866 internal register.
Input signal [14] of address selection sub-CPU CXD1866 internal register.
Terminal for power supply of 5 V withstand voltage. Supplies standard 5.0 V.
Not used.
Strobe negative logic input for register writing.
Strobe negative logic input for register state reading.
Strobe negative logic input for register status reading the chip inside the sub-CPU.
Digital ground terminal.
Standard 3.3 V digital power supply terminal.
Interrupt request negative logic output to sub-CPU from read channel block.
Interrupt request negative logic output to sub-CPU from decoder block and authentication block.
DRAM data bus [0].
DRAM data bus [1].
DRAM data bus [2].
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