Aiwa XD-PG700, Руководство по обслуживанию

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Pin No. Pin Name I/O Description
-57-
IC DESCRIPTION -5/5 (NDV8601 -4/7)
119 RSET O Current setting resistor of output DACs
120 COMP O Compensation capacitor connection
121 VSS P Core and Ring Ground
122 VIOCLK B VCLK input/output for Video I/O Port function
123 VSYNC B Bi-directional VSYNC signal for devices that do not use EAV/SAV codes; can be used as GPIO
124 HSYNC B
Bi-directional HSYNC signal for devices that do not use end active video/start active video (EAV/
SAV) codes; can be used as GPIO
125 VDDIO P I/O Pad power=3.3V
126 VIO[7]
B Bi-directional digital video port data bus; can be used as GPIO
127 VIO[6]
128 VIO[5]
129 VIO[4]
130 VIO[3]
131 VIO[2]
132 VSSIO P I/O Pad ground
133 VIO[1]
B Bi-directional digital video port data bus; can be used as GPIO
134 VIO[0]
135 VDD P Core Power=1.8V
136 AD[31] B µP multiplexed address/data bus 31
137 AD[30] B µP multiplexed address/data bus 30
138 AD[29] B µP multiplexed address/data bus 29
139 AD[28] B µP multiplexed address/data bus 28
140 VDDIO P I/O Pad power=3.3V
141 AD[27] B µP multiplexed address/data bus 27
142 AD[26] B µP multiplexed address/data bus 26
143 AD[25] B µP multiplexed address/data bus 25
144 AD[24] B µP multiplexed address/data bus 24
145 PWE[3] B
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
static random access memory (SRAM) or peripherals
146 AD[23] B µP multiplexed address/data bus 23
147 VSSIO P I/O Pad ground
148 AD[22] B µP multiplexed address/data bus 22
149 AD[21] B µP multiplexed address/data bus 21
150 AD[20] B µP multiplexed address/data bus 20
151 AD[19] B µP multiplexed address/data bus 19
152 AD[18] B µP multiplexed address/data bus 18
153 AD[17] B µP multiplexed address/data bus 17
154 VDDIO P I/O Pad power=3.3V
155 AD[16] B µP multiplexed address/data bus 16
156 PWE[2] B
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
static random access memory (SRAM) or peripherals
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