Pin No.
Pin Name
I/O
Description
-52-
I
I
–
–
–
I
–
–
–
O
O
O
O
O
–
–
O
I
I
I
Latch Enable for Software Mode/Sampling Rate Selection for Hardware Mode. When MODE
pin is LOW, ML is selected.(1)
Mode Control Select. When this pin is HIGH, device is operated in hardware mode using SR0
(pin 1), FS0 (pin 19), and FS1 (pin 20). When this pin is LOW, device is operated in software
mode by three-wire interface using ML (pin 1), MD (pin 19) and MC (pin 20).(1)
Digital Power Supply, +5V.
Digital Ground.
27MHz Crystal. When an external 27MHz clock is applied to XT1 (pin 6), this pin must be
connected to GND.
27MHz Oscillator Input/External 27MHz Input.
Ground for PLL.
Power Supply for PLL, +5V.
Reserved. Must be left open.
27MHz Output.
Inverted 27MHz Output.
Fixed 33.8688MHz Clock Output.
768f
S
Clock Output.
256f
S
Clock Output.
Digital Ground for VDDB.
Digital Power Supply for Clock Output Buffers, +3.3V.
384f
S
Output. This output has been optimized for the lowest jitter and should be connected to the
audio DAC(s).
Reset. When this pin is LOW, device is held in reset.(1)
Serial Data Input for Software Mode/Sampling Frequency Selection for Hardware Mode. When
MODE pin is LOW, MD is selected.(1)
Shift Clock Input for Software Mode/Sampling Frequency Selection for Hardware Mode. When
MODE pin is LOW, MC is selected.(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D PLL L
MODE
VDD
GND
XT2
XT1
GNDP
VDDP
RSV
MCKO
MPEG CLK
SCKO1 MCK
SCKO4
SCKO2
GNDB
VDDB
DA XCK
RESET
S DATA
S CLK
IC DESCRIPTION - 3/12 (PLL1700E)-1/1
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9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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