Aiwa RM-Z401P, Руководство по обслуживанию

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5-4
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
Pin Name
ACLK
MC DATA
SPDIF
ASDATA0
ASDATA1
ASDATA2
ASDATA3
ASDATA4
DACVDDC
VREF
FS
YUV0/CIN
DACVSSC
YUV1/C
DACVDDB
YUV2/Y
DACVSSB
YUV3/Y
DACVDDA
YUV4/G
DACVSSA
YUV5/B
YUV6/R
ICE
BLANK#
VSYN
YUV7
DVSS
HSYN
SPMCLK
SPDATA
DVDD2
SPLRCK
SPBCK
DVDD3
XTALO
XTALI
PRST
DVSS
VFO13
I/O
I
I
O
I
I
I
I
I
–
I
O
O
–
O
–
O
–
O
–
O
–
O
O
I
I
I
I
–
I
I
I
–
I
I
–
O
I
I
–
O
Function
Audio DAC master clock(384/256 audio sample freq.)
Microphone serial input
SPDIF output
Audio serial data 0 (Front L/R)
Audio serial data 1 (Rear L/R)
Audio serial data 2 (Center/Woofer)
Audio serial data 3 (Downmix L/R)
Trap value in power-on reset (DAC reset)
3.3V power pin for VIDEO DAC circuitry
Bandgap reference voltage
Full scale adjustment
Video data output bit 0
Compensation capacitor
Ground pin for VIDEO DAC circuitry
Video data output bit 1
Analog chroma output
3.3V power pin for VIDEO DAC circuitry
Video data output bit 2
Analog Y output
Ground pin for VIDEO DAC circuitry
Video data output bit 3
Analog composite output
3.3V power pin for VIDEO DAC circuitry
Video data output bit 4
Green or Y
Ground pin for VIDEO DAC circuitry
Video data output bit 5
Blue or Cb
Video data output bit 6
Red or Cr
Microcontroller ICE mode enable
Video blank area
Front U-com sub-request
Vertical sync
Audio mute
Video data output bit 7
Front U-com main-request
Ground pin for internal digital circuitry
Horizontal sync
16:9 signal
Audio DAC master clock of SPDIF input
Audio data of SPDIF input
2.5V power pin for internal digital circuitry
Audio left/right channel clock of SPDIF input
Audio bit clock of SPDIF input
Mic phone detect siganl
3.3V power pin for internal digital circuitry
Crystal output (27MHz)
Crystal input (27MHz)
Power on reset input, active high
Ground pin for internal digital circuitry
The 1st, 3rd header VFO pulse output