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Description
Pin No.
Pin Name
I/O
Synchronization signal detection output pin.
78
FSEQ
O
Outputs a high level when the synchronization signal detected from the EFM signal and the
internally generated synchronization signal agree.
79
DFECT
I/O
Defect pin. Which becomes an input pin after reset and can be controlled externally. This becomes
the defect monitor pin under control by command. (Not used)
80
EFMO
O
EFM signal output pin. (Not used)
Содержание NSX-VC8
Страница 12: ...SCHEMATIC DIAGRAM _ 1 MAIN 1 2 AMP SECTION 12 ...
Страница 13: ...SCHEMATIC DIAGRAM _ 2 MAIN 2 2 TUNER SECTION 13 ...
Страница 14: ...SCHEMATIC DIAGRAM _ 3 FRONT 14 ...
Страница 17: ...SCHEMATIC DIAGRAM _ 4 CD 1 2 CD LOAD CD DRIVE 17 ...
Страница 18: ...SCHEMATIC DIAGRAM _ 5 CD 2 2 18 ...
Страница 19: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H I J K L M N O P Q R S T U 19 WIRING 3 DECK ...
Страница 20: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H I J K L M N O P Q R S T U 20 WIRING 3 CD LOAD CD DRIVE ...
Страница 21: ... 21 FL HNA 10SS15T GRID ASSIGNMENT ANODE CONNECTION GRID ASSIGNMENT ANODE CONNECTION ...
Страница 22: ... 22 IC BLOCK DIAGRAM ...
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Страница 34: ... 34 CD TEST MODE ...
Страница 44: ...2 11 IKENOHATA 1 CHOME TAITO KU TOKYO 110 JAPAN TEL 03 3827 3111 Printed in Singapore 2000058 0251431 ...