Aiwa MVSD3NM, Руководство по обслуживанию

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Pin No. Pin Name I/O Description
IC DESCRIPTION-2/3 (ES3880)-1/2
VDD3
________
RAS
__________
DWE
MA0-MA8
DBUS0-DBUS15
_____________
RESET
GND
VDD3
YUV0-YUV7
VSYNC
HSYNC
CPUCLK
PCLK2X
PCLK
AUX0-AUX4
GND
VDD3
AUX6
AUX5
AUX7
LD0-LD7
__________
LWR
________
LOE
__________ _________
LCS3-LCS0
LA0-LA11
GND
VDD5
LA12-LA17
ACLK
AOUT/SELPLL1
ATCLK
—
O
O
O
I/O
I
—
—
O
I/O
I/O
I
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
O
O
O
O
—
—
O
I/O
O
I
I/O
Voltage supply for 3.3 V.
DRAM row address strobe. (active low)
DRAM write enable. (active low)
DRAM multiplexed row and column address bus.
DRAM data bus.
System reset. (active low)
Ground.
Voltage supply for 3.3 V.
Y is luminance, UV are chrominance data bus for screen video interface.
YUV [7: 0] for 8-bit YUV mode.
Vertical sync for screen video interface, programmable for rising or falling edge.
Horizontal sync for screen video interface, programmable for rising or falling edge.
RISC and system clock input.
CPUCLK is used only if SEL_PLL [1: 0] = 00.
Pixel clock; two times the actual pixel clock for screen video interface.
Pixel clock qualifier in for screen video interface.
Auxiliary control pins. (AUX0 and AUX1 are open collectors)
Ground.
Voltage supply for 3.3 V.
Auxiliary control pins.
Auxiliary control pins.
Auxiliary control pins.
RISC interface data bus.
RISC interface write enable. (active low) (Not connected)
RISC interface output enable. (active low)
RISC interface chip select. (active low)
RISC interface address bus.
Ground.
Digital supply voltage for 5 V.
RISC interface address bus.
Master clock for external audio DAC. (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344MHz,
and 18.432 MHz)
Dual-purpose pin. AOUT is the audio interface serial data output.
Pins SEL_PLL [1: 0] select phase-lock loop (PLL) clock frequency CPUCLK for the Visba:
00 = bypass PLL.
01 = 54 MHz PLL.
10 = 67.5 MHz PLL.
11 = 81 MHz PLL.
Audio transmit bit clock.