44
Pin No.
Pin Name
I/O
Description
Notes: PCMD is an MSB first, two's complement output.
GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection.
XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPCLK and the EFM signal transition point
coincide.
GFS goes high when the frame sync and the insertion protection timing match.
RFCK is derived from the crystal accuracy, and has a cycle of 136µ (during normal speed).
C2PO represents the data error status.
XRAOF is generated when the 16K RAM exceeds the ±48F jitter margin.
57
SCOR
O
Outputs a high signal when either subcode sync S0 or S1 is deteected. (Not used)
58
SBSO
O
Sub P to W serial output. (Not used)
59
EXCK
I
SBSO readout clock input. (Connected to GND)
60
VSS
GND.
61
VDD
Power supply (+5V).
62
SYSM
I
Mute input. Active when high. (Connected to GND)
63
AVSS
Analog GND.
64
AVDD
Analog power supply (+5V).
65
AOUT1
O
Left channel analog output.
66
AIN1
I
Left channel operational amplifier input.
67
LOUT1
O
Left channel LINE output.
68
AVSS
Analog GND.
69
XVDD
Power supply for master clock.
70
XTAI
I
Crystal oscillation circuit input. Input the external master clock via this pin.
71
XTAO
O
Crystal oscillation circuit output.
72
XVSS
GND for master clock.
73
AVSS
Analog GND.
74
LOUT2
O
Right channel LINE output.
75
AIN2
I
Right channel operational amplifier input.
76
AOUT2
O
Right channel analog output.
77
AVDD
Analog power supply (+5V).
78
AVSS
Analog GND.
79
XRST
I
System reset. Reset when low.
80
VDD
Power supply (+5V).
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Содержание CX-LMS5
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