Chapter 9
291
BERT
Bit Error Rate Tester–Option UN7
Figure 9-21
CH1: BER TEST OUT (pin 20 of AUX I/O connector)
CH2: BER MEAS END (pin 1 of AUX I/O connector)
In this example, the clock delay function is on. The rising edge of the clock was delayed by 200 ns and was
adjusted to the center of the data.
indicates the result of the using the clock delay function.
Figure 9-22
CH1
CH2
CH1
CH2
Содержание E4428C
Страница 22: ...Contents xxii ...
Страница 107: ...Chapter 3 83 Basic Operation Using Security Functions Figure 3 6 ESG Screen with Secure Display Activated ...
Страница 182: ...158 Chapter 4 Basic Digital Operation Using Waveform Clipping Figure 4 22 Rectangular Clipping ...
Страница 183: ...Chapter 4 159 Basic Digital Operation Using Waveform Clipping Figure 4 23 Reduction of Peak to Average Power ...
Страница 224: ...200 Chapter 4 Basic Digital Operation Creating and Using Bit Files ...
Страница 228: ...204 Chapter 5 AWGN Waveform Generator Configuring the AWGN Generator ...
Страница 229: ...205 6 Analog Modulation ...
Страница 276: ...252 Chapter 7 Digital Signal Interface Module Operating the N5102A Module in Input Mode ...
Страница 286: ...262 Chapter 8 Bluetooth Signals Turning On a Bluetooth Signal ...
Страница 287: ...263 9 BERT This feature is available only in E4438C ESG Vector Signal Generators with Option 001 601or 002 602 ...
Страница 330: ...306 Chapter 9 BERT Verifying BERT Operation ...
Страница 366: ...342 Chapter 10 CDMA Digital Modulation IS 95A Modulation ...
Страница 394: ...370 Chapter 12 Multitone Waveform Generator Applying Changes to an Active Multitone Signal ...
Страница 454: ...430 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Concepts Figure 15 9 Uplink Channel Structure ...
Страница 468: ...444 Chapter 15 W CDMA Digital Modulation for Component Test W CDMA Frame Structures ...
Страница 667: ...643 18 Troubleshooting ...
Страница 700: ...Index 676 Index ...